US 2017/0323898 A1 · SEMICONDUCTOR MEMORY DEVICE INCLUDING 3-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Claims16

Dependent claims

A semiconductor memory device comprising:

a substrate comprising cell regions and a contact region between the cell regions;
a dielectric structure formed over the contact region;
a memory block having cell parts, which are respectively formed over the cell regions, a coupling part, which is formed over the contact region and couples the cell parts, and a through part, which accommodates the dielectric structure;
a peripheral circuit formed over the substrate under the memory block;
bottom wiring lines disposed between the memory block and the peripheral circuit, the bottom wiring lines being electrically coupled with the peripheral circuit;
top wiring lines disposed over the memory block;
and
contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

5 more elements

A method for manufacturing a semiconductor memory device, comprising:

forming a peripheral circuit over a substrate comprising cell regions and a contact region between the cell regions;
forming bottom wiring lines over the peripheral circuit the bottom wiring lines being electrically coupled with the peripheral circuit;
stacking alternating layers of interlayer dielectric layers and sacrificial layers over the bottom wiring lines;
forming a first slit for dividing the interlayer dielectric layers and the sacrificial layers of the contact region into a first portion and a second portion, wherein the first portion is continuous with the interlayer dielectric layers and the sacrificial layers of the cell region, and the second portion is isolated from the first portion and the interlayer dielectric layers and the sacrificial layers of the cell region by the first slit, thereby form a dielectric structure constructed with the second portion;
forming a dielectric sidewall layer which fills the first slit;
forming a second slit through the interlayer dielectric layers and the sacrificial layers;
removing the sacrificial layers which are exposed by the second slit;
forming a conductive material in spaces from which the sacrificial layers are removed to thereby form conductive lines;
forming contact plugs electrically coupled with the bottom wiring lines, through the dielectric structure;
and
forming top wiring lines electrically coupled with the contact plugs.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

Life of this patent

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

Life of this patent

Abstract

Claims16