Semiconductor integrated circuits having contacts spaced apart from active regions

A semiconductor integrated circuit comprising:

• first and second active regions defined by an isolation layer on a substrate, the first and second active regions being doped with different types of impurities, the first and second active regions extending in a first direction, and the first and second active regions being spaced apart from each other in a second direction, the second direction being substantially perpendicular to the first direction;
• a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein
• the first and third gate structures are on the first active region and a first portion of the isolation layer between the first and second active regions, the first and third gate structures extend in the second direction, and the first and third gate structures are spaced apart from each other in the first direction, and
• the second and the fourth gate structures are on the second active region and the first portion of the isolation layer, the second and fourth gate structures extend in the second direction, the second and fourth gate structures are spaced apart from each other in the first direction, and the second and fourth gate structures face and are spaced apart from the first and third gate structures, respectively, in the second direction;
• a first contact, a second contact, a third contact, and a fourth contact, the first to fourth contacts being on portions of the first to fourth gate structures, respectively, wherein
• the first and fourth contacts are electrically connected to each other,
• the second and third contacts are electrically connected to each other,
• the first and third contacts are spaced apart from the first active region in the second direction by substantially the same distance, and
• the second and fourth contacts are spaced apart from the second active region in the second direction by substantially the same distance;
• a fifth gate structure on the first active region and the first portion of the isolation layer, the fifth gate structure extending in the second direction, and being spaced apart from the third gate structure in the first direction;
• and
• a sixth gate structure on the second active region and the first portion of the isolation layer, the sixth gate structure extending in the second direction, and being spaced apart from the fourth gate structure in the first direction, wherein
• the fifth and sixth gate structures are connected to each other on the first portion of the isolation layer, and
• the fifth and sixth gate structures extend in the second direction.

A semiconductor integrated circuit, comprising:

• first and second active regions defined by an isolation layer on a substrate, the first and second active regions being doped with different types of impurities, the first and second active regions extending in a first direction, and the first and second active regions being spaced apart from each other in a second direction, the second direction being substantially perpendicular to the first direction;
• a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein
• the first and third gate structures are on the first active region and a portion of the isolation layer adjacent to the first active region, the first and third gate structures extend in the second direction, and the first and third gate structures are spaced apart from each other in the first direction, and
• the second and fourth gate structures are on the second active region and a portion of the isolation layer adjacent to the second active region, the second and fourth gate structures extend in the second direction, the second and fourth gate structures are spaced apart from each other in the first direction, and the second and fourth gate structures face and are spaced apart from the first and third gate structures, respectively, in the second direction;
• a fifth gate structure on the first active region and the isolation layer, the fifth gate structure extending in the second direction, and being spaced apart from the third gate structure in the first direction;
• a sixth gate structure on the second active region and the isolation layer, the sixth gate structure extending in the second direction, and being spaced apart from the fourth gate structure in the first direction, wherein
• the fifth and sixth gate structures are connected to each other on a portion of the isolation layer between the first and second active regions,
• the fifth and sixth gate structures extend in the second direction,
• a seventh gate structure on the first active region and the isolation layer, the seventh gate structure extending in the second direction, and being spaced apart from the fifth gate structure in the first direction;
• an eighth gate structure on the second active region and the isolation layer, the eighth gate structure extending in the second direction, and being spaced apart from the sixth gate structure in the first direction, wherein
• the seventh and eighth gate structures are connected to each other on the portion of the isolation layer between the first and second active regions, and
• the seventh and eighth gate structures extend in the second direction;
• and
• a first contact, a second contact, a third contact, and a fourth contact, wherein
• the first to fourth contacts are on portions of the first to fourth gate structures, respectively,
• the first and fourth contacts are electrically connected to each other,
• the second and third contacts are electrically connected to each other,
• the first and third contacts are spaced apart from a boundary of the first active region in the second direction by substantially the same distance, and
• the second and fourth contacts are spaced apart from a boundary of the second active region in the second direction by substantially the same distance.

A method of manufacturing a semiconductor integrated circuit, the method comprising:

• forming an isolation layer on a substrate to define first and second active regions, the first and second active regions extending in a first direction and being spaced apart from each other in a second direction, the second direction being substantially perpendicular to the first direction;
• forming gate structures on the first active region, the second active region, and portions of the isolation layer, wherein
• first and third gate structures are formed on the first active region and a portion of the isolation layer adjacent to the first active region, the first and third gate structures extend in the second direction, and the first and third gate structures are spaced apart from each other in the first direction, and
• second and fourth gate structures are formed on the second active region and a portion of the isolation layer adjacent to the second active region, the second and fourth gate structures extend in the second direction, the second and fourth gate structures are spaced apart from each other in the first direction, and the second and fourth gate structures face and are spaced apart from the first and third gate structures, respectively, in the second direction;
• forming first, second, third, and fourth contacts on portions of the first, second, third, and fourth gate structures, respectively;
• electrically connecting the first and fourth contacts to each other;
• and
• electrically connecting the second and third contacts to each other, wherein
• the first and third contacts are spaced apart from the first active region in the second direction by substantially the same distance, and
• the second and fourth contacts are spaced apart from the second active region in the second direction by substantially the same distance.