Semiconductor integrated circuit and logic circuit
AssigneeSocionext Inc.
InventorHiroyuki SHIMBO
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.
Claims20
A standard cell having a NAND function, the standard cell comprising:
- first and second n-channel transistors connected together in series between an output node and a ground node, and
- first and second p-channel transistors connected together in parallel between the output node and a power supply node, wherein,
- the first n-channel transistor is comprised of n fin transistor(s) where n is an integer equal to or greater than one, the n fin transistor(s) having a same gate length and a same gate width, the first n-channel transistor having its gate connected to a first input node, and
- the second n-channel transistor is comprised of m fin transistors where m is an integer greater than n, the m fin transistors having the same gate length and the same gate width as the n fin transistor(s), the second n-channel transistor having its gate connected to a second input node, and
- the first p-channel transistor having its gate connected to the first input node, and
- the second p-channel transistor having its gate connected to the second input node.
A standard cell having a NAND function, the standard cell comprising:
- first and second n-channel transistors connected together in series between an output node and a ground node, and the first n-channel transistor is disposed closer to the output node than the second n-channel transistor, and
- first and second p-channel transistors connected together in parallel between the output node and a power supply node, wherein,
- the first n-channel transistor is comprised of n fin transistor(s) where n is an integer equal to or greater than one, the n fin transistor(s) having a same gate length and a same gate width, the first n-channel transistor having its gate connected to a first input node, and
- the second n-channel transistor is comprised of m fin transistors where m is an integer greater than n, the m fin transistors having the same gate length and the same gate width as the n fin transistor(s), the second n-channel transistor having its gate connected to a second input node, and
- the first p-channel transistor having its gate connected to the first input node, and
- the second p-channel transistor having its gate connected to the second input node.
Dependencies are inferred from the claim text.