Integrated circuit and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Te LIN, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Pin-Dai SUE, Li-Chun TIEN
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Abstract
A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
Claims20
An integrated circuit, comprising:
- a first cell comprising:
- at least one first active region;
- and
- at least one first gate electrode crossing the first active region;
- a second cell comprising:
- at least one second active region;
- and
- at least one second gate electrode crossing the second active region, wherein the first gate electrode and the second gate electrode are arranged end-to-end;
- and
- at least one dummy gate electrode partially present on edges of the first active region and the second active region, the dummy gate electrode being continuous at least between the first active region and the second active region.
An integrated circuit, comprising:
- at least one first active region;
- at least one first gate electrode crossing the first active region;
- at least one second active region;
- at least one second gate electrode crossing the second active region, the second gate electrode being disconnected with the first gate electrode;
- and
- at least one first dummy gate electrode partially present on edges of the first active region and the second active region, wherein a length of the first dummy gate electrode is greater than a length of the first gate electrode.
A method of configuring an integrated circuit layout using a processor, the method comprising:
- using the processor, choosing a plurality of cells from a cell library;
- using the processor, placing the cells on the integrated circuit layout, wherein the placing the cells forms at least one continuous PODE (poly on OD edge) on the integrated circuit layout, and the continuous PODE extends across at least one common boundary between the cells;
- generating a set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout;
- and
- storing the set of instructions in a non-transitory machine readable storage medium.
Dependencies are inferred from the claim text.