Stacked Semiconductor Structure and Method

A method comprising:

• depositing a first dielectric layer over a first chip comprising a plurality of first connection pads;
• patterning the first dielectric layer to form a plurality of first openings over the respective first connection pads;
• filling the plurality of first openings with a first conductive material to form a plurality of connectors over the respective first connection pads;
• forming a plurality of first bonding pads over the respective connectors, wherein a width of a first bonding pad is greater than a width of a corresponding connector;
• depositing a second dielectric layer over a second chip;
• patterning the second dielectric layer to form a plurality of second openings;
• filling the plurality of second openings with a second conductive material to form a plurality of second bonding pads in the second dielectric layer;
• and
• bonding the first chip and the second chip together to form a stacked chip structure through applying a thermal process to the first chip and the second chip and forming a homogenous layer between two adjacent bonding pads.

A method comprising:

• depositing a first dielectric layer over a first chip comprising a first substrate, a first interconnect structure over the first substrate, and a first connection pad over the first interconnect structure, wherein a top surface of the first connection pad is lower than a top surface of the first dielectric layer;
• patterning the first dielectric layer to form a first opening over the first connection pad;
• filling the first opening with a first conductive material to form a first bonding pad over the first connection pad, wherein a width of the first connection pad is greater than a width of the first bonding pad;
• depositing a second dielectric layer over a second chip comprising a second substrate and a second interconnect structure over the second substrate;
• patterning the second dielectric layer to form a second opening;
• filling the second opening with a second conductive material to form a second bonding pad, wherein a width of the second bonding pad is greater than the width of the first bonding pad;
• stacking the second chip on the first chip;
• and
• applying a hybrid bonding process to the first chip and a second chip to form a stacked chip device.