Nanoscale Interconnect Array for Stacked Dies

A microelectronic assembly, comprising:

• an insulating layer having a first surface and a second surface opposite the first surface;
• a plurality of nanoscale conductors disposed in an array within the insulating layer, the plurality of nanoscale conductors extending from the first surface to the second surface of the insulating layer, the array having a nanoscale pitch;
• one or more first microelectronic elements having a first face and a plurality of first element contacts at the first face, the first element contacts facing and joined to the plurality of nanoscale conductors at the first surface of the insulating layer;
• and
• one or more second microelectronic elements having a second face and a plurality of second element contacts at the second face, the second element contacts facing and joined to the plurality of nanoscale conductors at the second surface of the insulating layer, the plurality of nanoscale conductors forming electrical interconnections between first element contacts of the one or more first microelectronic elements and second element contacts of the one or more second microelectronic elements.

A method of fabricating a microelectronic assembly, comprising:

• forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;
• removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;
• filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;
• joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
• removing the substrate from the second surface of the insulating layer;
• joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer;
• forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors.

A method of fabricating a microelectronic assembly, comprising:

• forming an array of nanoscale conductors within an insulating layer on a substrate, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface, the array having a nanoscale pitch;
• joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
• removing the substrate from the second surface of the insulating layer;
• joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer;
• forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors.