Wafer level fan out semiconductor device and manufacturing method thereof

A semiconductor device comprising:

• a semiconductor die comprising a first surface, a second surface, third surfaces between the first surface and the second surface, a bond pad coupled to the first surface, and a passivation layer coupled directly to the first surface, the passivation layer having an opening that exposes the bond pad;
• a first sealing part coupled to the third surfaces of the semiconductor die;
• a conductive path extending from a first end coupled to the bond pad toward a second end, the second end directly in contact with a first surface of the first sealing part and positioned peripherally beyond the third surface of the semiconductor die;
• a conductive, interconnection structure coupled to the second end of the conductive path such that the interconnection structure is peripherally distributed beyond the third surface of the semiconductor die;
• and
• a second sealing part comprising a single layer on a surface of the first sealing part and the conductive path, and encapsulating at least 10% of a total height of the interconnection structure.

A method of forming a semiconductor device, the method comprising:

• forming a passivation layer over a first surface of the semiconductor die such that the passivation layer has an opening that exposes a bond pad on the first surface of the semiconductor die;
• encapsulating, with a first sealing part, a side surface of the semiconductor die that adjoins the first surface of the semiconductor die to an opposite second surface of the semiconductor die;
• forming a dielectric layer on the passivation layer and on the first sealing part;
• forming a conductive path on the first sealing part and dielectric layer such that the conductive path extends from a first end coupled to the bond pad toward a second end that is directly above the first sealing part and beyond the side surface of the semiconductor die;
• attaching a conductive, interconnection structure to the second end of the conductive path such that the interconnection structure is peripherally distributed beyond the third surface of the semiconductor die;
• and
• encapsulating the dielectric layer, the conductive path, and at least 10% of a total height of the interconnection structure with a second sealing part comprising a single layer.