Die edge crack and delamination detection

A die edge crack and delamination detection semiconductor package, comprising:

• a plurality of interconnected semiconductor devices, wherein each of the semiconductor devices includes an integrated circuit (IC) active area surrounded by at least one mechanical protection barrier (MPB);
• one or more metallization layers stacked on each of the IC active areas;
• a plurality of passive electronic devices placed within the one or more metallization layers at respective predetermined distances from each of the MPBs;
• and
• a detection circuit having circuitry configured to
• determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of each of the semiconductor devices,
• determine a lateral distance of a lead end of the crack or the delamination from each of the MPBs, and
• determine a rate of approach of the crack or the delamination encroaching towards each of the MPBs, wherein
• determining the specific metallization layer, the lateral distance, and the rate of approach are determined via a nominal change in an electrical measurement of at least one of the passive electronic devices within an associated semiconductor device for each of the semiconductor devices.

A method of detecting a crack or delamination, the method comprising:

• receiving a first electrical measurement reading, via a detection circuit of a semiconductor chip, from a first passive electronic device located within a first metallization layer of the semiconductor chip;
• determining whether the first electrical measurement reading is outside a first nominal designed range for the first passive electronic device;
• saving a location and time of the first electrical measurement reading for the first passive electronic device when the first electrical measurement reading registers outside of the first nominal designed range;
• receiving a second electrical measurement reading, via the detection circuit of the semiconductor chip, from a second passive electronic device located within a second metallization layer of the semiconductor chip, wherein the second electrical measurement reading registers outside of a second nominal designed range for the second passive electronic device;
• and
• determining a rate of progression from the first electrical measurement reading registering outside of the first nominal designed range and the second electrical measurement reading registering outside of the second nominal designed range.