Integrated circuit package having pin up interconnect

A method of fabricating an integrated circuit packaging, comprising the steps of:

• establishing a base;
• developing a plurality of electrical circuits using a first patterned conductive layer on the base, wherein an electrical circuit are formed by using a masking material;
• developing a stud conductive layer, where the stud conductive layer is disposed on at least one side of the first patterned conductive layer by developing a second layer photo-resist material on the masking material;
• removing the masking material and second layer photo-resist material;
• developing an encapsulating material from epoxy or polyimide compound on the base and exposed area of the stud conductive layer;
• grinding the surface area of the encapsulating material to level the surface of the stud conductive layer and the encapsulating material to form a flattened surface area;
• developing third photo-resist materials on the flat surface area of the surface of the stud conductive layer and the encapsulating material;
• developing a second electrically conductive layer on the leveled stud conductive layer by removing at least one part of the layers of third photo-resist materials;
• developing an isolation layer on the flat surface area of the surface of the stud conductive layer and the encapsulating material;
• grinding the surface area of the isolation layer to level the surface primer ink layer and the second electrically conductive layer;
• developing an conductive seed layer on grinded surface of the isolation layer and the second electrically conductive layer;
• developing a fourth photo-resist materials on the conductive seed layer;
• developing a third electrically conductive layer by removing at least one part of the layers of fourth photo-resist materials;
• etching the conductive seed layer or third electrically conductive layer or any combination thereof by using etching process;
• developing a masking layer on the third electrically conductive layer disposed on the conductive seed layer.
• developing a solder mask or epoxy compound or polyimide compound layer by removing at least one part of the masking layer;
• developing a fifth layer photo-resist material disposed on the surface of the solder masked surface and bottom portion of the base;
• and
• developing an opening on the patterned fifth layer photo-resist material located at bottom portion of the base for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of the first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.