Controller to detect malfunctioning address of memory device

A semiconductor memory device comprising:

• a plurality of primary data storage elements;
• a plurality of redundant data storage elements;
• and
• circuitry to:
• receive a first register setting command;
• initiate a repair mode in the semiconductor memory device in response to the first register setting command;
• receive an activation command, the activation command comprising an indication of a malfunctioning row address in the semiconductor memory device to be repaired;
• store the indication of the malfunctioning row address in one or more registers;
• receive a precharge command;
• receive a second register setting command;
• terminate the repair mode in the semiconductor memory device in response to the second register setting command;
• receive a memory access request for data stored at the malfunctioning row address;
• and
• redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

A method comprising:

• receiving, by circuitry of a semiconductor memory device, a first register setting command,
• initiating, by the circuitry, a repair mode in the semiconductor memory device in response to receiving the first register setting command;
• receiving, by the circuitry, an activation command, the activation command comprising an indication of a malfunctioning row address in a plurality of primary data storage elements in the semiconductor memory device to be repaired;
• storing, by the circuitry, the indication of the malfunctioning row address in one or more registers of the semiconductor memory device in response to receiving the activation command;
• receiving, by the circuitry, a precharge command;
• receiving, by the circuitry, a second register setting command;
• and
• terminating, by the circuitry, the repair mode in the semiconductor memory device in response to receiving the second register setting command;
• receiving a memory access request for data stored at the malfunctioning row address;
• and
• redirecting the memory access request to a corresponding row address in a plurality of redundant data storage elements.

A memory device comprising:

• a first plurality of data storage elements;
• a second plurality of data storage elements;
• and
• circuitry coupled with the first plurality of data storage elements and the second plurality of data storage elements, the circuitry comprising one or more registers and configured to:
• receive a first register setting command;
• initiate a repair mode in the memory device in response to the first register setting command;
• receive an activation command, the activation command comprising an indication of a malfunctioning address in the first plurality of data storage elements to be repaired;
• store the indication of the malfunctioning address in the one or more registers of the memory device in response to the activation command;
• receive a precharge command;
• and
• receive a second register setting command;
• terminate the repair mode in the memory device in response to the second register setting command;
• receive a memory access request for data stored at the malfunctioning row address;
• and
• redirect the memory access request to a corresponding row address in the second plurality of data storage elements.