US 2017/0323686 A1 · CHARGE INJECTION NOISE REDUCTION IN SAMPLE-AND-HOLD CIRCUIT

Abstract

A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.

Claims14

Dependent claims

An image sensor, comprising:

a pixel circuit configured to generate a pixel signal;
a vertical signal line configured to convey the pixel signal;
a sample-and-hold circuit configured to receive the pixel signal, the sample-and-hold circuit, including:
a first transistor,
a second transistor disposed between a gate and a drain of the first transistor,
a sampling capacitor, an electrode of the sampling capacitor being connected to the gate of the first transistor, and
a first current source connected to the drain of the first transistor;
and
a gate control circuit configured to provide a gate control signal to a gate of the second transistor,
wherein the gate control circuit includes an inverter configured to receive a supply voltage and an inverter control signal, and output the gate control signal.

7 more elements

Dependencies are inferred from the claim text.

Charge injection noise reduction in sample-and-hold circuit

Life of this patent

Charge injection noise reduction in sample-and-hold circuit

Life of this patent

Abstract

Claims14