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US 2017/0323683 A1Published application
Reconfigurable Sense Amplifier
AssigneeSTMicroelectronics (Rousset) SAS
InventorsFrançois Tailliet, Victorien Brecte
Life of this patent
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Abstract
A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
Claims24
A sense amplifier comprising:
- an output terminal;
- an input terminal;
- an input stage coupled to the input terminal;
- an output stage coupled to the output terminal;
- a first transistor coupled to a first supply terminal and having a control terminal coupled to an output of the input stage;
- a second transistor coupled to the first supply terminal;
- a mode input terminal coupled to a control node of the second transistor;
- a third transistor coupled to the second transistor and having a control terminal coupled to the output of the input stage;
- a fourth transistor coupled between the input terminal and a second supply terminal;
- and
- a fifth transistor coupled between the first transistor and the second supply terminal, the fifth transistor having a control terminal coupled to a control terminal of the fourth transistor.
8 more elements
A memory device comprising:
- a memory cell coupled to a bit line;
- a bit-line latch;
- and
- a sense amplifier comprising
- an output terminal,
- an input terminal coupled to an intermediate node via a first transistor, the intermediate node coupled to the memory cell via a second transistor and to an output of the bit-line latch,
- an input stage coupled to the input terminal,
- an output stage coupled to the output terminal,
- a third transistor coupled to a first supply terminal and having a control terminal coupled to an output of the input stage,
- a fourth transistor coupled to the first supply terminal,
- a mode input terminal coupled to a control node of the fourth transistor,
- a fifth transistor coupled to the fourth transistor and having a control terminal coupled to the output of the input stage.
9 more elements
A method comprising:
- at a first time, reading a memory cell coupled to a bit line with a sense amplifier comprising
- an output terminal,
- an input terminal coupled to an intermediate node via a first transistor, the intermediate node coupled to a memory cell via a second transistor and to an output of a bit-line latch,
- an input stage coupled to the input terminal,
- an output stage coupled to the output terminal,
- a third transistor coupled to a first supply terminal and having a control terminal coupled to an output of the input stage,
- a fourth transistor coupled to the first supply terminal,
- a mode input terminal coupled to a control node of the fourth transistor,
- a fifth transistor coupled to the fourth transistor and having a control terminal coupled to the output of the input stage, wherein reading the memory cell comprises
- receiving a signal at the mode input terminal, the signal having a first state,
- turning on the first transistor, and
- turning on the second transistor;
- and
- at a second time, reading the bit-line latch by:
- receiving the signal at the mode input terminal, the signal having a second state,
- turning on the first transistor, and
- turning off the second transistor.
14 more elements
Dependencies are inferred from the claim text.