Data output circuit and semiconductor memory device including the same

A semiconductor memory device comprising:

• a page buffer group suitable for storing bank data received from a plurality of banks in response to a read command;
• a data output circuit that is enabled in response to a bank selection signal, for storing the bank data received from the page buffer group in response to an input control signal, and for outputting the stored bank data to an input/output pad in response to an output control signal, wherein a first bit group of the bank data is delayed by a predetermined time and transferred as a first output data while a second bit group of the bank data is synchronized with a clock and transferred as a second output data;
• and
• a control logic suitable for generating the input control signal and the output control signal for performing a data output operation, and generating the bank selection signal by reflecting information of the clock.

A signal generation apparatus comprising:

• a first control signal generator suitable for generating a first control signal which is enabled in response to an address strobe signal, when an address signal representing a first bank is inputted;
• a second control signal generation unit suitable for generating a second control signal which is enabled in response to the address strobe signal, when the address signal representing a second bank is inputted;
• a flip-flop unit suitable for receiving a clock at a clock terminal, the first control signal at a reset terminal, an inverted signal of the second control signal at a set terminal, and an inverted output signal of the flip-flop unit at an input terminal;
• and
• a clock information reflecting unit suitable for generating the first selection signal and the second selection signal by reflecting information of the clock into the inverted output signal and the output signal of the flip-flop unit.