Memory controller with phase adjusted clock for performing memory operations
AssigneeRambus Inc.
InventorsIan P. Shaeffer, Lei Luo
Life of this patent
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Abstract
In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
Claims20
An Apparatus comprising:
- an interface circuit comprising:
- a pad for coupling the apparatus to a data bus;
- a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal;
- and
- a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal,
- wherein the interface circuit uses the first phase adjusted clock signal to read data via the pad during a first read operation and uses the second phase adjusted clock signal to read data via the pad during a second read operation after the first read operation.
A method of operation in an apparatus coupled to a data bus via a pad of the apparatus, the method comprising:
- generating a first phase adjusted clock signal from at least one clock signal;
- generating a second phase adjusted clock signal from at least one clock signal;
- and
- reading data via the pad during a first read operation using the first phase adjusted clock signal;
- and
- reading data via the pad during a second read operation after the first read operation using the second phase adjusted clock signal.
An apparatus comprising:
- an interface circuit comprising:
- a pad for coupling the apparatus to a data bus;
- a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal;
- and
- a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal,
- wherein the interface circuit uses the first phase adjusted clock signal to write data via the pad during a first write operation and uses the second phase adjusted clock signal to write data via the pad during a second write operation after the first write operation.
A method of operation in an apparatus coupled to a data bus via a pad of the apparatus, the method comprising:
- generating a first phase adjusted clock signal from at least one clock signal;
- generating a second phase adjusted clock signal from at least one clock signal;
- and
- writing data via the pad during a first write operation using the first phase adjusted clock signal;
- and
- writing data via the pad during a second write operation after the first write operation using the second phase adjusted clock signal.
Dependencies are inferred from the claim text.