Sense amplifier
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
InventorsFrancesco La Rosa, Gineuve Alieri
Life of this patent
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Abstract
A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
Claims21
A method of operating a sense amplifier, the method comprising:
- pre-charging a first and second bit lines of a memory device with respective first and second pre-charging circuits during a pre-charge phase, wherein the first pre-charging circuit is coupled to a first input terminal of the sense amplifier via a first switch and the second pre-charging circuit is coupled to a second input terminal of the sense amplifier via a second switch;
- charging a capacitive network of the sense amplifier during an initial phase, wherein the capacitive network comprises
- a first capacitor coupled between the first input terminal and a first supply node of a second logic gate of a latch, the first supply node of the second logic gate coupled to a first power supply terminal via a third switch, and
- a second capacitor coupled the second input terminal and a first supply node of a first logic gate of the latch, the first supply node of the first logic gate coupled to the first power supply terminal via a fourth switch, the second logic gate of the latch having an output coupled to an input of the first logic gate of the latch, and an input coupled to an output of the first logic gate of the latch;
- raising respective voltages of the first supply nodes of the first and second logic gates by opening the third and fourth switches after charging the capacitive network and during the initial phase;
- sensing, during a sensing phase and after the initial phase, a difference between slopes of signals present at the first and second input terminals by closing the first and second switches;
- and
- latching, during a latching phase and after the sensing phase, data in the first and second logic gates by closing the third and fourth switches.
A sense amplifier comprising:
- a first supply terminal;
- a second supply terminal;
- a first inverter having
- an input,
- an output,
- a first supply node coupled to the first supply terminal via a first switch, and
- a second supply node coupled to the second supply terminal via a second switch;
- a second inverter having
- an input coupled to the output of the first inverter,
- an output coupled to the input of the first inverter,
- a first supply node coupled to the first supply terminal via a third switch, and
- a second supply node coupled to the second supply terminal via a fourth switch;
- a fifth switch coupled between the input of the first inverter and the output of the first inverter;
- a first input terminal coupled to the second supply node of the second inverter via a first capacitor;
- a second input terminal coupled to the second supply node of the second inverter via a second capacitor;
- a first output terminal coupled to the output of the first inverter;
- and
- a second output terminal coupled to the output of the second inverter.
A memory device comprising:
- a first and second bit lines;
- a pre-charging circuit configured to pre-charge the first and second bit lines during a pre-charge phase;
- and
- a sense amplifier comprising a first and second input terminals coupled to the first and second bit lines, a latch, and a capacitive network coupled to a first and second power supply nodes of the latch, the sense amplifier configured to
- charge the capacitive network by connecting the capacitive network to a first and second power supply terminals,
- float the latch by disconnecting the first and second power supply terminals from the capacitive network after charging the capacitive network,
- sense a difference between slopes of signals present at the first and second input terminals while the latch is floating, and
- latching data in the latch based on the difference between slopes by connecting the first and second power supply terminals to the capacitive network.
Dependencies are inferred from the claim text.