Memories having select devices between access lines and in memory cells formed of a same type of circuit element
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
Estimating the term…
Abstract
Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of the plurality of memory cells may be connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells may include a respective second select device, of a plurality of second select devices, and a respective programmable element, of a plurality of programmable elements, connected in series, and the first select device and each second select device of the plurality of second select devices may each be formed of a same type of circuit element.
Claims20
A memory, comprising:
- a first select device connected between a first access line and a second access line;
- and
- a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines;
- wherein each memory cell of the plurality of memory cells comprises a respective second select device, of a plurality of second select devices, and a respective programmable element, of a plurality of programmable elements, connected in series;
- and
- wherein the first select device and each second select device of the plurality of second select devices are each formed of a same type of circuit element.
A memory, comprising:
- a first select device connected between a first access line and a second access line;
- a second select device connected between the first access line and the second access line;
- and
- a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines;
- wherein each memory cell of the plurality of memory cells comprises a respective third select device, of a plurality of third select devices, and a respective variable resistive element, of a plurality of variable resistive elements, connected in series;
- and
- wherein the first select device, the second select device, and each third select device of the plurality of third select devices are each formed of a same type of non-ohmic device.
A memory, comprising:
- a first diode connected between a first access line and a second access line;
- a second diode connected between a third access line and a fourth access line;
- and
- a plurality of memory cells;
- wherein each memory cell of the plurality of memory cells comprises a respective third diode, of a plurality of third diodes, and a respective programmable element, of a plurality of programmable elements, connected in series;
- wherein each memory cell of a first subset of the plurality of memory cells is connected between the second access line and a respective fifth access line of a plurality of fifth access lines;
- wherein each memory cell of a second subset of the plurality of memory cells, mutually exclusive of the first subset of the plurality of memory cells, is connected between the fourth access line and a respective fifth access line of the plurality of fifth access lines;
- and
- wherein the first diode, the second diode, and each third diode of the plurality of third diodes are configured to be biased in a same direction in response to a particular bias applied to the first access line and to the third access line and a different bias applied to each fifth access line of the plurality of fifth access lines.
Dependencies are inferred from the claim text.