Unit shift register circuit, shift register circuit, control method for unit shift register circuit, and display device

A unit shift register circuit constituting each stage of a shift register circuit, the unit shift register circuit comprising:

• a first transistor that comprises a first gate terminal, a first source terminal, and a first drain terminal, inputs a predetermined clock signal to the first drain terminal, and outputs an output signal from the first source terminal;
• a second transistor that comprises a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, inputs a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal;
• and
• a third transistor that comprises a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, inputs a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal,
• wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and
• wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

A control method for a unit shift register circuit that constitutes each stage of a shift register circuit,

• wherein the unit shift register circuit comprises,
• a first transistor that comprises a first gate terminal, a first source terminal, and a first drain terminal, inputs a predetermined clock signal to the first drain terminal, and outputs an output signal from the first source terminal;
• a second transistor that comprises a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, inputs a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal;
• and
• a third transistor that comprises a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, inputs a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal,
• wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and
• wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

A display device comprising:

• a plurality of pixels;
• a plurality of scanning lines to which the plurality of pixels are connected;
• and
• a plurality of unit shift register circuits respectively constituting stages of a shift register circuit, each of the plurality of unit shift register circuits comprising:
• a first transistor that comprises a first gate terminal, a first source terminal, and a first drain terminal, inputs a predetermined clock signal to the first drain terminal, and outputs an output signal from the first source terminal;
• a second transistor that comprises a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, inputs a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal;
• and
• a third transistor that comprises a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, inputs a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal,
• wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and
• wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.