Method for triple-patterning friendly placement

An article of manufacture comprising a non-transitory computer readable medium having computer program logic stored thereon that, when executed by a computing device, causes the computing device to perform operations for triple-patterning placement, the operations comprising:

• identifying one or more triple-patterning design rule checking (DRC) violations in a placement region;
• inserting one or more placement blockages based on the identified one or more triple-patterning design rule checking violations;
• placing a plurality of cells in a chip design to provide a design layout;
• and
• outputting the design layout to a machine readable storage medium, wherein the outputted layout being configured to manufacture a set of masks used in integrated circuit fabrication processes.

A system for generating a detailed placement, the system comprising:

• a memory that stores instructions for triple-patterning placement;
• a processor configured to:
• identify a cell with one or more triple-patterning DRC violations in at least one of a vertical direction or a horizontal direction;
• insert one or more placement blockages based on the identified one or more triple-patterning design rule checking violations;
• place a plurality of cells in a chip design to provide a design layout;
• and
• output the design layout to a machine readable storage medium, wherein the outputted design layout is configured to manufacture a set of masks used in integrated circuit fabrication processes.