Method and system for designing fpga based on hardware requirements defined in source code

A non-transitory machine-readable medium having instructions stored therein, which when executed by a processor, cause the processor to perform operations of designing FPGA, the operations comprising:

• parsing a source code to identify a first routine to perform a first function and a second routine to perform a second function;
• determining a control signaling topology between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code;
• allocating a first logic block describing a first hardware configuration representing the first function of the first routine;
• allocating a second logic block describing a second hardware configuration representing the second function of the second routine;
• and
• generating a register-transfer level (RTL) netlist based on the first logic block and the second logic block, wherein the second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.

A data processing system for searching images for mobile devices, the system comprising:

• a processor;
• and
• a memory coupled to the processor storing instructions, which when executed by the processor, cause the processor to perform operations of programming FPGA, the operations including
• parsing a source code to identify a first routine to perform a first function and a second routine to perform a second function,
• determining a control signaling topology between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code,
• allocating a first logic block describing a first hardware configuration representing the first function of the first routine,
• allocating a second logic block describing a second hardware configuration representing the second function of the second routine, and
• generating a register-transfer level (RTL) netlist based on the first logic block and the second logic block, wherein the second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.