Dma controller with arithmetic unit
AssigneeNXP USA, Inc.
InventorsMICHAEL GALDA, WANGSHENG MEI, MARTIN MIENKINA
Life of this patent
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Abstract
A digital signal processor (DSP) includes a CPU, and a DMA controller. The DMA controller transfers data from a source to a destination as a function of an initialization command from the CPU. The DMA controller has a logic unit that performs filter operations and other arithmetic operations on-the-fly on a data stream transferred therethrough. The filter operations include multiplication by filter coefficients and addition, without processing by the CPU. The DMA controller may have subsets of hardware configurations that can perform different operations that are selectable as a function of the initialization command.
Claims15
A digital signal processor, comprising:
- a central processor unit (CPU);
- a main system memory;
- and
- a direct memory access (DMA) controller that couples the CPU to the main system memory, the DMA controller for transferring data from a source memory address to a destination memory address as a function of an initialization command from the CPU, the DMA controller comprising:
- a logic unit for performing filter operations on-the-fly on a data stream transferred by way of the DMA controller from the source memory address to the destination memory address, wherein the filter operations include multiplication by filter coefficients and addition without processing by the CPU.
In a digital signal processor having a central processor unit (CPU) and a direct memory access (DMA) controller for transferring data between a source and a destination as a function of an initialization command from the CPU, the DMA controller comprising:
- a plurality of DMA input channels and at least one DMA output channel;
- an arithmetic unit for performing arithmetic operations on-the-fly on data transferred through the DMA controller;
- wherein the arithmetic unit has a plurality of subsets of hardware configurations for performing different arithmetic operations, including at least one of addition, subtraction, multiplication, division, square root operations, and combinations thereof on data on a plurality of the DMA input channels;
- wherein the DMA controller selects at least one of the subsets as a function of the initialization command from the CPU;
- wherein the DMA controller performs the at least one selected operation and sends an interrupt to the CPU when the transfer of data and the at least one selected operation are complete;
- wherein the arithmetic unit includes a multiplier and an accumulator, and the arithmetic operations include multiply-accumulate (MAC) filter operations, and the filter operations include multiplication by filter coefficients and addition without processing by the CPU;
- input and output registers for storing historic values of the data stream;
- and
- a look-up table (LUT) memory for storing the filter coefficients.
Dependencies are inferred from the claim text.