Synchronous input/output computer system including hardware invalidation of synchronous input/output context

A computer program product, the computer program product comprising a computer readable storage medium having program instructions for purging a device table cache (DTC) included in a synchronous input/output (I/O) computing system, the program instructions executable by a processor to perform:

• issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a device table entry transaction, the device table entry transaction having a total data length to be transferred;
• selecting a device table entry from a device table, loading the entry into the DTC, and transferring data packets corresponding to the device table entry transaction using the selected device table entry;
• monitoring, via a host bridge processor, the data packets transferred using the selected table entry;
• and
• automatically purging the selected device table entry from the DTC, via the host bridge processor, in response to determining the transferred data packets match the total data length.

A synchronous input/output (I/O) computing system comprising a processor and a memory unit that stores program instructions, the system configured to purge a device table cache (DTC) in response to the processor executing the program instructions to perform:

• issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a device table entry transaction, the device table entry transaction having a total data length to be transferred;
• selecting a device table entry from a device table, loading the entry into the DTC, and transferring data packets corresponding to the device table entry transaction using the selected device table entry;
• monitoring, via a host bridge processor, the data packets transferred using the selected table entry;
• and
• automatically purging the selected device table entry from the DTC, via the host bridge processor, in response to determining the transferred data packets match the total data length.