Method to control cache replacement for decoupled data fetch
AssigneeNVIDIA Corporation
InventorsRonny Meir Krashinsky, Xiaogang Qiu
Life of this patent
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Abstract
A method, computer readable medium, and system are disclosed for decoupling data pre-fetch from demand loads. The method includes the steps of receiving, by a processor, a set of instructions that includes a load instruction; and executing, by the processor, the load instruction to perform a load operation. The load operation loads data from a cache unit into a register file. The load instruction includes a no-update operator that prevents the cache unit from updating the cache state information in response to the load operation. The result is that the eviction policy for the cache unit responds to the order of pre-fetch memory access requests rather than the demand load operations.
Claims20
A method, comprising:
- receiving a set of instructions to be executed by a processor that includes a cache unit, wherein at least one instruction in the set of instructions includes a load instruction;
- and
- executing the load instruction configured to perform a load operation, wherein the load instruction includes a no-update operator that prevents the cache unit from updating cache state information corresponding to an eviction policy for a cache line specified by the load instruction in response to the load operation.
A non-transitory, computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:
- receiving a set of instructions to be executed by a processor that includes a cache unit, wherein at least one instruction in the set of instructions includes a load instruction;
- and
- executing the load instruction configured to perform a load operation, wherein the load instruction includes a no-update operator that prevents the cache unit from updating cache state information corresponding to an eviction policy for a cache line specified by the load instruction in response to the load operation.
A system, comprising:
- a processor configured to:
- receive a set of instructions to be executed by a processor that includes a cache unit, wherein at least one instruction in the set of instructions includes a load instruction, and
- execute the load instruction configured to perform a load operation, wherein the load instruction includes a no-update operator that prevents the cache unit from updating cache state information corresponding to an eviction policy for a cache line specified by the load instruction in response to the load operation.
Dependencies are inferred from the claim text.