Reducing minor garbage collection overhead
AssigneeInternational Business Machines Corporation
InventorsTatsuhiro Chiba, Hiroshi Horii, Tamiya Onodera
Life of this patent
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Abstract
A method and system are provided for reducing garbage collection overhead. The method includes representing, by a hardware processor, an application program by a Directed Acyclic Graph having a set of nodes. Each of the nodes represents a respective one of a plurality of computation tasks. The method further includes specifying, by the hardware processor from the set of nodes, any of the nodes which store a respective computation result for at least a threshold period of time as cache nodes. The method further includes allocating, by the hardware processor, the respective computation result of each of the cache nodes into a tenure area of a memory.
Claims20
A method for reducing garbage collection overhead, comprising:
- representing, by a hardware processor, an application program by a Directed Acyclic Graph having a set of nodes, each of the nodes representing a respective one of a plurality of computation tasks;
- specifying, by the hardware processor from the set of nodes, any of the nodes which store a respective computation result for at least a threshold period of time as cache nodes;
- and
- allocating, by the hardware processor, the respective computation result of each of the cache nodes into a tenure area of a memory.
A non-transitory computer readable storage medium comprising a computer readable program for reducing garbage collection overhead, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
- representing, by a hardware processor, an application program by a Directed Acyclic Graph having a set of nodes, each of the nodes representing a respective one of a plurality of computation tasks;
- specifying, by the hardware processor from the set of nodes, any of the nodes which store a respective computation result for at least a threshold period of time as cache nodes;
- and
- allocating, by the hardware processor, the respective computation result of each of the cache nodes into a tenure area of a memory.
A system, comprising:
- a memory partitioned into a nursery area and a tenure area;
- a hardware processor configured to:
- represent an application program by a Directed Acyclic Graph having a set of nodes, each of the nodes representing a respective one of a plurality of computation tasks;
- specify, from the set of nodes, any of the nodes which store a respective computation result for at least a threshold period of time as cache nodes;
- and
- allocate the respective computation result of each of the cache nodes into the tenure area of a memory.
Dependencies are inferred from the claim text.