Debugging support unit for microprocessor
AssigneeSTMicroelectronics (Beijing) R&D Co., Ltd.
InventorsXiao Kang JIAO, PengFei ZHU
Life of this patent
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Abstract
A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.
Claims20
A debug-enabled processing device, comprising:
- a processor;
- a communication transceiver circuit;
- and
- a debug support unit, the debug support unit having a plurality of dedicated debug registers that facilitate debugging a software program under execution by the processor, the plurality of debug registers including:
- a control register having at least four bits, the at least four bits including control bits to enable/disable a plurality of debugging operations;
- and
- a set of index registers, the set of index registers configurable to pass data to and from the processor.
A debugging method performed via a target device, the target device having a processor, a communication transceiver circuit, and a debug support unit, the debug support unit having a plurality of dedicated debug registers, the method comprising:
- writing a first value to a control register of the dedicated debug registers to enable a debug mode of the target device;
- writing a second value to the control register of the dedicated debug registers to suspend an execution of instructions of a program being debugged;
- polling the control register of the dedicated debug registers for a signal indicating that the processor has flushed any instructions that were in an execution pipeline of the processor before suspending execution of the instructions of the program being debugged;
- passing data to or from registers of the processor via a set of index registers of the dedicated debug registers;
- and
- writing a second value to the control register of the dedicated debug registers to disable the debug mode of the target device.
An embedded processing system, comprising:
- a processor means for executing software instructions of a target program;
- a transceiver means for communicating first data between the embedded processing system and an external host computing device;
- and
- a debug support unit means for directing debug operations on the target program, the debug support means including:
- a control register means for enabling and disabling a plurality of debugging operations;
- and
- an index register means for passing second data to and from the processor.
Dependencies are inferred from the claim text.