Pipelined cascaded digital signal processing structures and methods
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Claims21
1-25. (canceled)
Cascaded circuitry operable in floating-point mode or in fixed-point mode, comprising:
- a first circuit, comprising:
- a first output port,
- a first input port,
- a first arithmetic circuit coupled to the first input port, and
- a plurality of pipeline registers disposed in connection with the first arithmetic circuit;
- a second circuit, comprising:
- a second output port, and
- a second input port;
- and
- a cascade register coupled between the first output port and the second input port, wherein the cascade register is selectively bypassed when the first circuit is operated in the fixed-point mode.
A method of operating cascaded circuitry that is operable in floating-point mode or in fixed-point mode, wherein the cascaded circuitry comprises first and second circuits that are coupled via a cascade register, wherein the first circuit comprises:
- a first output port,
- a first input port,
- a first arithmetic circuit coupled to the first input port, and
- a plurality of pipeline registers disposed in connection with the first arithmetic circuit,
- and wherein the second circuit comprises:
- a second output port, and
- a second input port,
- the method comprising:
- receiving a data input signal at the first input port;
- transmitting the data input signal via the first arithmetic circuit and the plurality of pipeline registers to the first output port;
- receiving, from a processor, a first command signal to operate the first circuit in floating-point mode and to use the cascade register;
- and
- in response to the first command signal:
- transmitting, via the cascade register, an interblock data signal from the first output port to the second input port.
An integrated circuit with a plurality of DSP blocks that are arranged in a cascade chain and that are each operable in fixed-point mode or in floating-point mode, comprising:
- a first DSP block of the plurality of DSP blocks, comprising:
- a first output,
- a first input,
- a first arithmetic operator circuit coupled to the first input, and
- pipeline registers disposed in connection with the first arithmetic operator circuit;
- a second DSP block of the plurality of DSP blocks, comprising:
- a second output, and
- a second input;
- and
- a cascade connection between the first output and the second input, comprising:
- a cascade register that is selectively bypassed when the first DSP block is operated in the fixed-point mode.
Dependencies are inferred from the claim text.