Low-power processor with support for multiple precision modes

A method, comprising:

• receiving, at a processor having a register size of a second wordlength, an indication of whether data is low-precision data of a first wordlength or high-precision data of the second wordlength that is longer than the first wordlength;
• processing, by the processor, the data as data aligned to most significant bits in registers of the processor in the low-precision mode;
• and
• detecting, by the processor, saturation during the processing of the data, wherein the same saturation point is examined whether the data is low-precision data or high-precision data.

An apparatus, comprising:

• a digital signal processor (DSP) configured to process data with a first wordlength in a first mode and to process data with a second wordlength longer than the first wordlength in a second mode, wherein a register size of the digital signal processor (DSP) matches the second wordlength, the digital signal processor (DSP) configured to perform steps comprising:
• processing data aligned to most significant bits of registers of the digital signal processor (DSP) in the first mode;
• and
• detecting saturation during the processing of the data in the first mode, wherein the same saturation point is examined whether the processor is operating in the first mode or the second mode.

A computer program product, comprising:

• a non-transitory computer readable medium comprising code for performing steps comprising:
• receiving an indication of whether data is low-precision data of a first wordlength or high-precision data of a second wordlength that is longer than the first wordlength;
• processing the data as data aligned to most significant bits in the low-precision mode;
• and
• detecting saturation during the processing of the data, wherein the same saturation point is examined whether the data is low-precision data or high-precision data.

A method, comprising:

• processing first data in a first mode having a first wordlength using a datapath of a processor;
• and
• processing second data in a second mode having a second wordlength that is longer than the first wordlength using the datapath of the processor,
• wherein the step of processing the first data in the first mode comprises processing the first data as data aligned to most significant bits of the datapath.