Performing Rounding Operations Responsive To An Instruction

A processor comprising:

• a plurality of registers including a first register and a second register;
• a control register having a first field to indicate a current floating point round mode, and a second field to indicate whether denormals are to be converted to zero;
• a status register having a third field to store a value, the value to indicate whether an inexact exception has occurred;
• a control unit to receive a round instruction and to decode fields of the round instruction, the round instruction to identify the first register, which is to store a source operand with a plurality of packed double precision floating point values, the round instruction to indicate that the current floating point round mode is to be used, and the round instruction to indicate to suppress a change in the value of the third field of the status register;
• and
• an execution unit coupled to the control unit, and coupled to the plurality of registers, the execution unit, responsive to the round instruction, to:
• convert a denormal of the source operand to zero when the second field indicates that said denormals are to be converted to zero;
• perform a round operation according to the current floating point round mode, to generate integral valued packed double precision floating point values that correspond to the packed double precision floating point values of the source operand;
• and
• store the integral valued packed double precision floating point values in the second register.