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US 2017/0322801 A1Published application
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
AssigneeTexas Instruments Incorporated
InventorsKenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
Life of this patent
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Abstract
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
Claims13
A process of operating an electronic circuit, the process comprising:
- supplying a varying counter value in a programmable range;
- and
- responding to a first instruction to program the range and responding to a second instruction having an associated operand to repeatedly vary said operand in an operand value range determined as a function of the counter value varying in the programmable range.
A process of operating a processor having a pipeline for electronic computing, the process comprising:
- successively delivering a repeat instruction and a repeating instruction having an operand;
- responding to the repeat instruction to program an operand value range;
- and
- responding to said repeated instruction and its operand to repeatedly vary the value of said operand in said operand value range and to deliver the repeatedly varied value of said operand to the pipeline.
1 more element
An electronic circuit comprising:
- a memory;
- a set of longer width and shorter width storage elements;
- an instruction operand value generating circuit operable to generate a succession of values in an operand value range;
- an address pipeline coupled to said instruction operand value generating circuit and operable to use the succession of values to access a succession of memory locations in the memory;
- and
- selection circuitry also coupled to said instruction operand value generating circuit and operable to concurrently use the same succession of values to access the set of longer width and shorter width storage elements and thereby effectuate transfers of information between said set and said memory.
3 more elements
A processing system comprising:
- a printed circuit board;
- a volatile memory;
- a processor on said printed circuit board for electronic computing coupled to said volatile memory and said processor including a pipeline and a set of longer width and shorter width storage elements;
- a nonvolatile memory elsewhere on said printed circuit board and coupled to said processor, for holding representations of instructions for said instruction register to save and restore the set of longer width and shorter width storage elements to said volatile memory, the instructions including a repeat instruction as well as a repeated instruction having an operand;
- said processor further including:
- an instruction operand value generating circuit operable to generate values varying in an operand value range and biasedly related to said operand of the repeated instruction represented in said nonvolatile memory;
- and
- selection circuitry in said pipeline coupled to said instruction operand value generating circuit and operable to use the values to access said set of longer width and shorter width storage elements, and thereby facilitate transfers of information between said set and said volatile memory.
5 more elements
An electronic debugging circuit comprising:
- a bias value generator circuit operable to supply a varying bias value in a programmable range and having a counter register;
- a pipeline register;
- an instruction circuit responsive to a first instruction to program the range of said bias value generator circuit and further responsive to a second instruction having an operand to repeatedly issue said second instruction to said pipeline register with said operand varied in an operand value range determined as a function of the varying bias value;
- and
- a scan controller having at least one scan path linking said counter register and said pipeline register to said scan controller.
2 more elements
A process of manufacturing comprising:
- fabricating structures on an integrated circuit wafer defining both a bias value generator circuit having a programmable range and an instruction circuit coupled to said bias value generator circuit;
- and
- electrically testing said structures to verify that said instruction circuit is responsive to a first instruction to program the range of said bias value generator circuit and that the bias value generator circuit supplies a varying bias value in the programmed range and that the instruction circuit is further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
Dependencies are inferred from the claim text.