Internally truncated multiplier
AssigneeTexas Instruments Incorporated
InventorsJawaharlal TANGUDU, Suvam NANDI, Pooja SUNDAR, Jaiganesh BALAKRISHNAN
Life of this patent
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Abstract
A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
Claims19
A multiplier circuit, comprising:
- a partial product generation circuit configured to generate a plurality of partial products for multiplying two values;
- a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products;
- and
- a summation circuit coupled to the truncation circuit, the summation circuit configured to sum the truncated partial products produced by the truncation circuit.
A digital down converter (DDC), comprising:
- a mixer configured to multiply samples of a received radio frequency signal with samples of a down conversion frequency to produce an intermediate frequency signal, the mixer comprising:
- a multiplier to multiply the samples of the radio frequency signal with the samples of the down conversion frequency, the multiplier comprising:
- a partial product generation circuit configured to generate a plurality of partial products for multiplying a sample of the radio frequency signal and a sample of the down conversion frequency;
- a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some of the partial products by removing a least significant bit from the at least some of partial products;
- and
- a summation circuit coupled to the truncation circuit, the summation circuit configured to sum the truncated partial products produced by the truncation circuit.
A multiplier circuit, comprising:
- a partial product generation circuit configured to generate a plurality of partial products for multiplying two values;
- a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some of the partial products by removing a least significant bit from the at least some of partial products;
- a bias compensation circuit configured to:
- determine a bias introduced in a multiplication by operation of the truncation circuit;
- and
- generate a bias compensation value to offset the determined bias;
- a summation circuit coupled to the truncation circuit and the bias compensation circuit, the summation circuit configured to:
- sum the truncated partial products produced by the truncation circuit;
- and
- add the bias compensation value to a sum of the truncated partial products.
Dependencies are inferred from the claim text.