Back to results
US 2017/0322772 A1Published application
Method for a stage optimized high speed adder
AssigneeIntel Corporation
InventorMohammad Abdallah
Life of this patent
Estimating the term…
Abstract
A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.
Claims18
A method implemented by a parallel adder, the method comprising:
- receiving a set of one bit inputs in parallel;
- adding the set of one bit inputs in parallel in a first stage and second stage of the parallel adder to generate an output that is a sum of the set of one bit inputs, the output being a non-redundant value, the first stage including at least one four to one adder and the second stage including at least one three to two carry save adder.
A parallel adder circuit, the parallel adder circuit comprising:
- a first stage to receive a set of one bit inputs in parallel, first stage to add the set of one bit inputs in parallel and output a set of sums to a second stage, the first stage including at least one four to one adder;
- and
- the second stage to generate an output that is a sum of the set of one bit inputs, the output being a non-redundant value, the second stage including at least one three to two carry save adder.
A processor to perform parallel adding, the processor comprising:
- an interconnect to enable communication within the processor;
- a set of execution units coupled to the interconnect to execute instructions;
- and
- at least one arithmetic unit including a first stage to receive a set of one bit inputs in parallel, first stage to add the set of one bit inputs in parallel and output a set of sums to a second stage, the first stage including at least one four to one adder, and the second stage to generate an output that is a sum of the set of one bit inputs, the output being a non-redundant value, the second stage including at least one three to two carry save adder.
1 more element
Dependencies are inferred from the claim text.