Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks

A method for operating a specialized processing block that is configurable to perform fixed-point arithmetic operations and floating-point arithmetic operations, comprising:

• receiving first, second, third, and fourth input signals at first, second, third, and fourth input ports, respectively;
• using first configurable interconnect circuitry to select first and second multiplicands among the first, second, and third input signals and route the first and second multiplicands to an arithmetic operator circuit;
• using second configurable interconnect circuitry to select first and second summands among the second and fourth input signals and an arithmetic operator circuit output signal from the arithmetic operator circuit and route the first and second summands to a floating-point adder circuit and a fixed-point adder circuit;
• and
• using third configurable interconnect circuitry to select an output signal among a floating-point adder circuit output signal from the floating-point adder circuit, a fixed-point adder circuit output signal from the fixed-point adder circuit, and the arithmetic operator circuit output signal from the arithmetic operator circuit and route the output signal to an output port.

An integrated circuit, comprising:

• a specialized processing block that is configurable to perform fixed-point arithmetic operations and floating-point arithmetic operations and comprises:
• first, second, third, and fourth input ports that receive first, second, third, and fourth input signals, respectively,
• an output port,
• an arithmetic operator circuit that generates a product signal based on first and second multiplicand signals,
• a floating-point adder circuit,
• a fixed-point adder circuit,
• first configurable interconnect circuitry coupling the first, second, and third input ports to the arithmetic operator circuit, wherein the first configurable interconnect circuitry is configured to select the first and second multiplicands among the first, second, and third input signals and route the first and second multiplicands to the arithmetic operator circuit,
• second configurable interconnect circuitry coupling the arithmetic operator circuit and the second and fourth input ports to the floating-point adder circuit and the fixed-point adder circuit, and
• third configurable interconnect circuitry coupling the floating-point adder circuit, the fixed-point adder circuit, and the arithmetic operator circuit to the output port.