Data Flow Control For Multi-Chip-Select

A system for performing communication between a host and a plurality of endpoints that are activated by chip select, the apparatus comprising:

• a common First In, First Out (FIFO) buffer for data transfer in a first direction, each entry in the FIFO buffer comprising a data location and a tag location, wherein a value of the tag location is operable to be set to either a designation of available or an identifier for a respective endpoint;
• and
• a plurality of registers associated with respective endpoints, the registers comprising an access register for read or write triggering a corresponding operation to the FIFO buffer.

A non-transitory computer-readable medium having a sequence of program instructions which, when executed by a processor, perform a method of operating a First In, First Out FIFO buffer that transfers data between a master device and a plurality of endpoints using chip select, said method comprising:

• receiving a current value of a read pointer and a status for an active endpoint;
• and
• reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.