Memory access techniques in memory devices with multiple partitions
AssigneeMicron Technology, Inc.
InventorsShekoufeh Qawami, Rajesh Sundaram
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
Claims25
A memory device, comprising:
- a first memory partition including a first plurality of memory locations;
- a second memory partition including a second plurality of memory locations;
- and
- an operation instruction decoder to decode a received instruction as a next partition command to perform a memory access at a same memory location of the second memory partition as a previous memory location of a previous memory access of the first memory partition.
A method of operating a memory system, comprising:
- identifying a same memory location in each of a first memory partition and a second memory partition for consecutive memory access commands, the first memory partition and second memory partition contained in a memory array;
- sending a memory access command to the memory array that identifies the memory location at the first memory partition and a function to be performed;
- and
- sending a next partition command to the memory array that indicates the same memory location and function as in the memory access command are to be used at the second memory partition.
A method of operating a memory device, comprising:
- receiving, at the memory device, a memory access command that identifies a memory location at a first memory partition of the memory device and a function to be performed;
- accessing, at the first memory partition, the memory location and performing the function;
- receiving, at the memory device, a next partition command;
- and
- accessing, at a second memory partition of the memory device, the memory location received in the memory access command and performing the function received in the memory access command.
An apparatus for data transfer, comprising:
- a memory array coupled with a control/address (C/A) bus and a data bus, the memory array comprising a plurality of memory partitions including at least a first memory partition and a second memory partition;
- and
- a controller coupled with the C/A bus and the data bus in electronic communication with the memory array, wherein the controller is operable to:
- identify a same memory location in each of the first memory partition and the second memory partition for consecutive memory access commands;
- send, via the C/A bus, a memory access command to the memory array that identifies the memory location at the first memory partition and a function to be performed;
- receive, via the data bus, data associated with the memory location at the first memory partition;
- and
- send, via the C/A bus, a next partition command to the memory array that indicates the same memory location and function as in the memory access command are to be used at the second memory partition.
Dependencies are inferred from the claim text.