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US 2017/0322726 A1Published application
Non-deterministic memory protocol
AssigneeMicron Technology, Inc.
InventorsRobert M. Walker, James A. Hall, JR., Frank F. Ross
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.
Claims31
An apparatus, comprising:
- a memory device;
- and
- a controller coupled to the memory device configured to:
- perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations.
1 more element
An apparatus comprising:
- a memory device;
- and
- a controller coupled to the memory device configured to:
- receive a first read command from a host;
- send a first read ready signal to the host in response to the controller having data associated with the first read command ready to send to the host;
- receive a first read send signal from the host in response to the host receiving the first read ready signal from the controller, wherein the host can send the first read send signal any time the host is ready to receive the data associated with the first read command;
- and
- send the data associated with the first read command and a first read identification (RID) signal to the host on a data bus in response to receiving the first read send signal.
5 more elements
An apparatus, comprising:
- a memory device;
- and
- a controller coupled to the memory device configured to:
- receive a first write command from a host;
- receive data associated with the first write command from the host on a data bus after a first write data transfer time period associated with the first write command;
- and
- send a first write count increment signal to the host in response to writing the data associated with the first write command.
4 more elements
A method, comprising:
- sending an activate command and a read command from a host to a memory device;
- sending a read ready signal from the memory device to the host in response to the memory device having data associated with the read command ready to send to the host;
- sending a read send signal from the host to the memory device in response to receiving the read ready signal from the memory device;
- and
- sending the data associated with the read command from the memory device to the host in response to receiving the read send signal from the host.
2 more elements
A method, comprising:
- sending a first write command from a host to memory device;
- receiving data associated with the first write command at the memory device from the host on a data bus after a first write data transfer time period associated with the first write command;
- and
- sending a first write count increment signal to the host in response to writing the data associated with the first write command to the memory device.
1 more element
Dependencies are inferred from the claim text.