Two-dimensional array of cmos control elements

An electronic device comprising:

• a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising a semiconductor device, the plurality of CMOS control elements comprising:
• a first subset of CMOS control elements comprising a PMOS semiconductor device portion, the PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device;
• a second subset of CMOS control elements comprising an NMOS semiconductor device portion, the NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device;
• wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the first subset of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the first subset of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the second subset of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the second subset of CMOS control elements.

An electronic device comprising:

• a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising semiconductor devices, the plurality of CMOS control elements each comprising:
• a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device;
• and
• an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device;
• a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements;
• and
• an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion;
• wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.