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US 2017/0322236 A1Published application
Wafer inspection method
AssigneeTokyo Seimitsu Co., Ltd.
InventorsYuichi OZAWA, Yasuhito IGUCHI, Tetsuo YOSHIDA, Junzo KOSHIO
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AssigneeTokyo Seimitsu Co., Ltd.
InventorsYuichi OZAWA, Yasuhito IGUCHI, Tetsuo YOSHIDA, Junzo KOSHIO
Estimating the term…
A wafer inspection method whereby inspection accuracy and operation efficiency is improved. A method for performing electrical inspection by bringing, at one time, a plurality of probes into contact with a plurality of pads in chips on a wafer. A chuck step S1 for heating the wafer to an inspection temperature; a first position recognition step S2 for recognizing all the positions of the pads of the chips; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the position of the pads for the purpose of recognizing the positional shifts of the pads due to thermal expansion when the wafer chuck is heated; and a correction step S4 for correcting contact positions with respect to the probes, the contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.
A wafer inspection method which simultaneously brings a plurality of probes disposed on a probe card into contact with a plurality of pads being on chips on a wafer to perform an electrical inspection, comprising:
A wafer inspection method using probes disposed on a probe card contacting pads on chips on a wafer for performing an electrical inspection, comprising the steps of:
Dependencies are inferred from the claim text.