CMOS Compatible BioFET
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAlexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
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Abstract
The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
Claims20
A bioFET device, comprising:
- a FET device on a semiconductor substrate, wherein the FET device includes a gate structure formed on a first surface of the semiconductor substrate and a channel region within the semiconductor substrate wherein the channel region interposes a source region and a drain region in the semiconductor substrate;
- an isolation layer having an opening and disposed on a second surface of the semiconductor substrate, the second surface being parallel to and opposing the first surface, wherein the opening exposes the channel region of the FET device, the channel region including a portion of the second surface of the semiconductor substrate;
- an interface material on the channel region of the second surface of the semiconductor substrate in the opening;
- a multi-layer interconnect (MLI) structure on the first surface of the semiconductor substrate, wherein the MLI structure includes at least a first conductive layer and a second conductive layer interposed by an inter-layer dielectric (ILD);
- and
- a carrier substrate coupled to the first conductive layer of the MLI structure.
A bioFET device, comprising:
- a FET device on a first semiconductor substrate, wherein the FET device includes a gate structure formed on a first surface of the first semiconductor substrate and a channel region within the first semiconductor substrate wherein the channel region interposes a source region and a drain region in the first semiconductor substrate;
- an isolation layer having an opening and disposed on a second surface of the first semiconductor substrate, the second surface being parallel to and opposing the first surface, wherein the opening exposes the channel region of the FET device, the channel region including a portion of the second surface of the first semiconductor substrate;
- an interface material on the channel region of the second surface of the first semiconductor substrate in the opening;
- a multi-layer interconnect (MLI) structure on the first surface of the first semiconductor substrate, wherein the MLI structure includes at least a first conductive layer and a second conductive layer interposed by an inter-layer dielectric (ILD);
- and
- a second semiconductor substrate coupled to the first conductive layer of the MLI structure.
A bioFET device, comprising:
- a FET device on a semiconductor substrate, wherein the FET device includes a gate structure formed on a first surface of the semiconductor substrate and a channel region within the semiconductor substrate wherein the channel region interposes a source region and a drain region in the semiconductor substrate;
- an isolation layer having an opening and disposed on a second surface of the semiconductor substrate, the second surface being parallel to and opposing the first surface, wherein the opening exposes the channel region of the FET device, the channel region including a portion of the second surface of the semiconductor substrate;
- a multi-layer interconnect (MLI) structure on the first surface of the semiconductor substrate, wherein the MLI structure includes at least a first conductive layer and a second conductive layer interposed by an inter-layer dielectric (ILD);
- and
- a carrier substrate having a conductive trace, wherein the conductive trace is electrically coupled to the first conductive layer of the MLI structure, and wherein a portion of the semiconductor substrate is removed to expose a portion of the conductive trace.
Dependencies are inferred from the claim text.