Maximum likelihood detector and wireless signal receiver with maximum likelihood detection function

A maximum likelihood detector (ML detector) configured to execute maximum likelihood detection (ML detection) according to one of a reception signal and a derivative thereof and according to one of a channel estimation signal and a derivative thereof, the ML detector comprising:

• a search value selecting circuit configured to select a first search value and a second search value, each of which is not less than a predetermined threshold;
• and
• a maximum likelihood detecting circuit (ML detecting circuit) configured to execute at least the following steps:
• selecting K1 first-layer bit-one candidate signal values according to the first search value, one of the reception signal and the derivative thereof, and one of the channel estimation signal and the derivative thereof, in which the K1 is an integer greater than one;
• calculating K1 second-layer bit-zero candidate signal values according to the K1 first-layer bit-one candidate signal values;
• selecting K2 first-layer bit-zero candidate signal values according to the second search value, one of the reception signal and the derivative thereof, and one of a swap signal of the channel estimation signal and a derivative of the swap signal, in which the K2 is an integer greater than one;
• calculating K2 second-layer bit-one candidate signal values according to the K2 first-layer bit-zero candidate signal values;
• and
• calculating log likelihood ratios (LLRs) according to the K1 first-layer bit-one candidate signal values, the K1 second-layer bit-zero candidate signal values, the K2 first-layer bit-zero candidate signal values and the K2 second-layer bit-one candidate signal values.

A wireless signal receiver with a maximum likelihood detection function (ML detection function), comprising:

• a Discrete Fourier Transform (DFT) circuit configured to convert a time-domain signal into a frequency-domain signal;
• a reference signal extraction circuit configured to generate an extraction reference signal according to the frequency-domain signal;
• a channel estimation circuit configured to generate a channel estimation signal according to the extraction reference signal;
• a data signal extraction circuit configured to generate an extraction data signal according to the frequency-domain signal;
• a signal detecting circuit configured to generate a detection signal according to the channel estimation signal and the extraction data signal, the signal detecting circuit including a maximum likelihood detector (ML detector) configured to execute at least the following steps:
• determining a first-layer search value;
• and
• a maximum likelihood detection step including:
• selecting K first-layer candidate signal values according to the first-layer search value, one of the extraction data signal and a derivative thereof, and one of the channel estimation signal and a derivative thereof, in which the K is an integer greater than one;
• calculating K second-layer candidate signal values according to the K first-layer candidate signal values;
• determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer;
• when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal value(s) according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) as at least a part of the detection signal according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s);
• and
• when the decision result is negative, calculating LLRs as at least a part of the detection signal according to the K first-layer candidate signal values and the K second-layer candidate signal values;
• and
• a decoding circuit configured to generate a decoded signal according to the detection signal.