Pll for carrier generator and method of generating carrier signals
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFeng Wei KUO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO, William Wu SHEN
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFeng Wei KUO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO, William Wu SHEN
Estimating the term…
A phase locked loop (PLL) for a carrier generator includes a front-end circuit that receives a frequency reference signal and generates a control signal based on the frequency reference signal and a feedback signal. A demultiplexer selectively outputs the control signal to a plurality of tuning arrangements. The plurality of tuning arrangements includes a first tuning arrangement that generates a first carrier signal based on the control signal and a second tuning arrangement that generates a second carrier signal based on the control signal. A multiplexer outputs the feedback signal based on the first carrier signal and the second carrier signal.
A phase locked loop (PLL) for a carrier generator, the PLL comprising:
A carrier generator comprising:
A method of generating a plurality of carrier signals, the method comprising:
Dependencies are inferred from the claim text.