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US 2017/0317680 A1Published application
Ratioed logic with a high impedance load
AssigneeHewlett-Packard Development Company, L.P.
InventorsNing Ge, Boon Bing Ng, Leong Yap Chia
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Abstract
A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.
Claims15
A device having ratioed logic with a high impedance load, comprising:
- an output;
- a pull-down network serially-coupled between a first voltage and the output;
- and
- a high impedance load serially-coupled between a second voltage and the output;
- in which the high impedance load is smaller than a transistor of the pull-down network.
2 more elements
A system having ratioed logic with a high impedance load, comprising:
- a first voltage;
- a second voltage;
- an output;
- a number of n-channel metal-oxide-semiconductor field effect transistors (NMOSs) serially-coupled between the first voltage and the output;
- and
- a high impedance load serially-coupled between the second voltage and the output,
- in which the high impedance load is disposed on top of a drain of a transistor.
4 more elements
A method for forming ratioed logic with a high impedance load, comprising:
- forming a first metal-oxide-semiconductor field-effect transistor (MOSFET) on a substrate;
- forming a second MOSFET on the substrate;
- and
- forming a high impedance load on top of a drain of the second MOSFET;
- in which:
- a source of the second MOSFET and a drain of the first MOSFET are shared;
- a drain of the first MOSFET is encompassed by a source of the first MOSFET;
- and
- a drain of the second MOSFET is encompassed by a source of the second MOSFET.
6 more elements
Dependencies are inferred from the claim text.