Semiconductor circuit

A semiconductor circuit, comprising:

• a first node that has a logic level value different from a logic level of an enable signal or a logic level of a scan enable signal, when a clock signal is at a first logic level;
• a second node in which a value is determined by the logic level of the first node when the clock signal is at the first logic level, and the value is maintained by a logic level of a third node when the clock signal is at a second logic level;
• a third node in which a value is determined by the logic level of the second node;
• and
• a fourth node in which a value is determined by the logic level of the second node when the clock signal is at the second logic level,
• wherein the fourth node is discharged through a first transistor gated to a voltage level of the second node to provide a ground voltage to the fourth node, and a second transistor gated to a voltage level of the clock signal to electrically connect the third node and the fourth node.

A semiconductor circuit, comprising:

• a first logic gate that receives input of a clock signal, an enable signal or a scan enable signal and performs a first logic operation to output a first output signal to a first node;
• a second logic gate that receives input of the first output signal of the first logic gate, the clock signal and a signal of a third node and performs a second logic operation to output a second output signal to a second node;
• a first transistor and a second transistor that are gated to a voltage level of the second output signal of the second logic gate and connected in series with each other to determine a value of the third node;
• a third logic gate that receives input of the second output signal of the second logic gate and the clock signal and performs a third logic operation to output a third output signal to a fourth node;
• and
• a third transistor that is gated to a voltage level of the clock signal to electrically connect the third node and the fourth node.