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US 2017/0317672 A1Published application
Power-On-Reset Circuit
AssigneeArm Limited
InventorsLalit Gupta, Vivek Nautiyal, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar, Vivek Asthana
Life of this patent
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Abstract
Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.
Claims20
A circuit comprising:
- a memory circuit having a first latch;
- and
- a power-on-reset circuit having a second latch coupled to the first latch,
- wherein the second latch is configured to reset the first latch to a predetermined state at power-up,
- wherein the second latch comprises a NAND SR latch having at least one inverter and multiple NAND dates arranged to receive a first Q signal from the first latch and provide a second Q signal to the first latch, and
- wherein the power-on-reset circuit further comprises a delay circuit that provides a forward biasing signal to at least one of the multiple NAND gates of the NAND SR latch.
3 more elements
A circuit comprising:
- a memory circuit having a first latch;
- and
- a power-on-reset circuit having a second latch and a delay circuit arranged to reset the first latch to a predetermined state at power-up,
- wherein the second latch comprises a NAND SR latch having at least one inverter and multiple NAND gates arranged to receive a first Q signal from the first latch and provide a second Q signal to the first latch, and
- wherein the delay circuit provides a forward biasing signal to at least one of the multiple NAND gates of the NAND SR latch.
2 more elements
A circuit comprising:
- a memory circuit having a latch;
- and
- a power-on-reset circuit having a delay circuit coupled to the latch,
- wherein the delay circuit comprises multiple inverters that are configured to reset the latch to a predetermined state at power-up, and
- wherein one or more inverters of the multiple inverters are arranged to provide a forward biasing voltage as a source supply voltage to at least one other inverter of the multiple inverters.
2 more elements
Dependencies are inferred from the claim text.