Flip-flop with delineated layout for reduced footprint

A flip-flop disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate, the flip-flop comprising:

• scan mux input circuitry made up of a first plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region;
• and
• slave switch circuitry operably coupled to an output of the scan mux input circuitry, the slave switch circuitry being made up of a second plurality of devices that are circumscribed by a slave switch perimeter;
• the slave switch perimeter residing within the flip-flop region and being non-overlapping with the scan mux perimeter.

A flip-flop disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate, the flip-flop comprising:

• scan mux input circuitry made up of a first plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region;
• and
• master switch circuitry operably coupled to an output of the scan mux input circuitry, the master switch circuitry being made up of a second plurality of devices that are circumscribed by a master switch perimeter;
• the master switch perimeter residing within the flip-flop region and being non-overlapping with the scan mux perimeter.