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US 2017/0302438 A1Published application
Advanced bus architecture for aes-encrypted high-performance internet-of-things (iot) embedded systems
AssigneeThe Florida International University Board of Trustees
InventorsXiaokun Yang, Jean H. Andrian
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Abstract
Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.
Claims17
A device, comprising:
- a control bus having a single master;
- and
- a data bus, in operable communication with the control bus, having a single slave providing connectivity between the single master of the control bus, memory, and an encryption/decryption engine.
A method of performing data transfer, the method comprising:
- adopting an Advanced Encryption Standard (AES) state as the basic unit of data transfer;
- processing state data during the transfer in column-major order;
- performing a READ operation into an encryption engine by cyclic-shift of the plaintext state data;
- and
- performing a WRITE operation into a decryption engine by cyclic-inverse-shift of the ciphtertext state data.
2 more elements
Dependencies are inferred from the claim text.