Pipelined cascaded digital signal processing structures and methods
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Claims19
Circuitry accepting a data input and generating a data output based on said data input, said circuitry comprising:
- a first circuit block, including:
- a first multiplier circuit,
- a first plurality of pipeline registers that pipeline an operation of the first multiplier circuit,
- a first adder circuit accepting a first adder input from within the first circuit block and a second adder input from a first interblock connection;
- and
- a second circuit block cascaded to the first circuit block via the first interblock connection, including:
- a second multiplier circuit,
- a second plurality of pipeline registers that pipeline an operation of the second multiplier circuit, wherein the second plurality of pipeline registers has a first selectable connection configuration such that one or more of the second plurality of pipeline registers are configured to be selectively bypassed to balance the first adder input and the second adder input.
A method for operating circuitry that includes first and second circuit blocks having respective first and second multiplier circuits and respective first and second adder circuits, and wherein the second circuit block is cascaded to the first circuit block via an interblock connection, comprising:
- receiving a first data signal at a first plurality of pipeline registers in the first circuit block, wherein the first plurality of pipeline registers pipeline an operation of the first multiplier circuit;
- transmitting the first data signal through the first plurality of pipeline registers to a first adder input of the first adder circuit;
- receiving a second data signal at a second plurality of pipeline registers in the second circuit block, wherein the second plurality of pipeline registers pipeline an operation of the second multiplier circuit;
- transmitting the second data signal through the second plurality of pipeline registers and the interblock connection to a second adder input of the first adder circuit;
- and
- configuring a selectable connection in the second circuit block to selectively bypass one or more of the second plurality of pipeline registers to balance the first adder input and the second adder input.
An integrated circuit, comprising:
- first, second, and third DSP blocks that each comprise a multiplier circuit, an adder circuit, and a plurality of pipeline registers that pipeline an operation of the multiplier circuit, wherein
- a first interblock connection couples the first and the second DSP blocks,
- a second interblock connection couples the second and the third DSP blocks,
- the adder circuit in the first DSP block accepts a first adder input from within the first DSP block, and a second adder input from the first interblock connection, and
- a selectable connection in the second DSP block is configured such that one or more of the plurality of pipeline registers in the second DSP block are selectively bypassed to balance the first and second adder inputs.
Dependencies are inferred from the claim text.