# US 2017/0288705 A1 · Shared memory with enhanced error correction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288705 A1 - Document ID: US20170288705A1 - Status: Published application - Kind: A1 - Application number: 15/091,195 - Filed: 2016-04-05 - Published: 2017-10-05 - Earliest claimed: 2016-04-05 - Assignees: Alibaba Group Holding Limited - Applicants: Alibaba Group Holding Limited - Inventors: Shu LI - Web page: https://patentgrep.com/patent/US20170288705A1 ## CPC - H03M 13/2927: {Decoding strategies} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 13/4068: {Electrical coupling} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/2909: {Product codes} - H03M 13/2948: {Iterative decoding (H03M13/2957 takes precedence)} - G11C 2029/0411: {Online error correction} - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H03M 13/1515: {Reed-Solomon codes} - H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system that detects and corrects bit errors performs a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit. The memory system further determines the first decoding procedure regarding the serial unit was not successful and performs the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units. The serial unit and the plurality of additional serial units constitute a predefined grouping of the encoded data. The memory system also performs a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units. Each successive bit in each of the plurality of derivative units is correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units. ## Claims ### Claim 1 A device for detecting and correcting bit errors, comprising: a memory that stores machine instructions; and a processor coupled to the memory that executes the machine instructions to perform a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit, determine whether or not the first decoding procedure regarding the serial unit was successful, in response to determining the first decoding procedure regarding the serial unit was not successful, perform the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units, the serial unit and the plurality of additional serial units comprising a predefined grouping of the encoded data, and perform a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units, each successive bit in each of the plurality of derivative units correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units, wherein the serial unit and the additional serial units each includes a predetermined quantity of sequential bits. ### Claim 2 (depends on 1) The device of claim 1, wherein the processor further executes the machine instructions to determine whether or not the second decoding procedure regarding the plurality of derivative units was successful, perform a first iterative decoding procedure regarding a series of serial units corresponding to the plurality of decoded derivative units to produce an updated series of decoded serial units based on having determined the second decoding procedure regarding the plurality of derivative units was not successful, determine whether or not the first iterative decoding procedure regarding the series of serial units was successful, and perform a second iterative decoding procedure regarding a second plurality of derivative units to produce an updated plurality of decoded derivative units based on having determined the first iterative decoding procedure regarding the series of serial units was not successful, each successive bit in each of the second plurality derivative units correlated to a corresponding sequential position in each of the updated series of decoded serial units. ### Claim 3 (depends on 2) The device of claim 2, wherein the processor further executes the machine instructions to continue to perform the first iterative decoding procedure regarding successive resulting series of serial units and the second iterative decoding procedure regarding successive resulting derivative units until the encoded data is successfully decoded, and send the decoded serial unit corresponding to the successful resulting series of serial units to a host computer. ### Claim 4 (depends on 2) The device of claim 2, wherein the processor further executes the machine instructions to store the updated series of decoded serial units in a buffer, store the updated plurality of decoded derivative units in the buffer, determine one of the first iterative decoding procedure and the second iterative decoding procedure was successful, and send the decoded serial unit corresponding to the updated series of decoded serial units to a host computer. ### Claim 5 (depends on 1) The device of claim 1, wherein the processor further executes the machine instructions to read the serial unit from a series of memory cells in a memory, wherein the serial unit corresponds to a page of stored data in the memory and the grouping corresponds to a block of stored data in the memory. ### Claim 6 (depends on 1) The device of claim 1, wherein the processor further executes the machine instructions to encode a series of segments of user data to produce a plurality of extensions of parity bits, each extension of the plurality of extensions of parity bits based on a respective segment in the series, append each of the plurality of extensions of parity bits to the respective segment to form the serial unit of the encoded data and the plurality of additional serial units of the encoded data, wherein the serial unit and the plurality of additional serial units include a plurality of row codewords, encode a plurality of derivative segments to produce a plurality of pendent strings of parity bits, each successive bit in each of the plurality of derivative segments correlated to a corresponding sequential position in the serial unit and each of the additional serial units, concatenate individual bits corresponding to consecutive sequential positions in each of the pendent strings of parity bits to form parity segments, the plurality of derivative segments and the corresponding plurality of pendent strings of parity bits forming the plurality of derivative units, wherein each of the plurality of derivative units include a plurality of column codewords, and send the plurality of row codewords and the plurality of column codewords to the memory. ### Claim 7 (depends on 1) The device of claim 1, wherein the first decoding procedure implements an error correction code and the second decoding procedure implements the error correction code. ### Claim 8 (depends on 1) The device of claim 1, wherein the first decoding procedure implements a first error correction code and the second decoding procedure implements a second error correction code that differs from the first error correction code. ### Claim 9 (depends on 1) The device of claim 1, wherein the memory comprises a plurality of dynamic random-access memory (DRAM) dual in-line memory modules (DIMMs) coupled to a plurality of memory cards configured in accordance with a Peripheral Component Interconnect Express (PCIe or PCI-E) standard. ### Claim 10 A method of detecting and correcting bit errors, comprising: performing a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit; determining the first decoding procedure regarding the serial unit was not successful; performing the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units, the serial unit and the plurality of additional serial units comprising a predefined grouping of the encoded data; and performing a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units, each successive bit in each of the plurality of derivative units correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units, wherein the serial unit and the additional serial units each includes a predetermined quantity of sequential bits. ### Claim 11 (depends on 10) The method of claim 10, further comprising: determining whether or not the second decoding procedure regarding the plurality of derivative units was successful; performing a first iterative decoding procedure regarding a series of serial units corresponding to the plurality of decoded derivative units to produce an updated series of decoded serial units based on having determined the second decoding procedure regarding the plurality of derivative units was not successful; determining whether or not the first iterative decoding procedure regarding the series of serial units was successful; and performing a second iterative decoding procedure regarding a second plurality of derivative units to produce an updated plurality of decoded derivative units based on having determined the first iterative decoding procedure regarding the series of serial units was not successful, each successive bit in each of the second plurality derivative units correlated to a corresponding sequential position in each of the updated series of decoded serial units. ### Claim 12 (depends on 11) The method of claim 11, further comprising: continuing to perform the first iterative decoding procedure regarding successive resulting series of serial units and the second iterative decoding procedure regarding successive resulting derivative units until the encoded data is successfully decoded; and sending the decoded serial unit corresponding to the successful resulting series of serial units to a host computer. ### Claim 13 (depends on 11) The method of claim 11, further comprising: storing the updated series of decoded serial units in a buffer; storing the updated plurality of decoded derivative units in the buffer; determining one of the first iterative decoding procedure and the second iterative decoding procedure was successful; and sending the decoded serial unit corresponding to the updated series of decoded serial units to a host computer. ### Claim 14 (depends on 10) The method of claim 10, further comprising reading the serial unit from a series of memory cells in a memory, wherein the serial unit corresponds to a page of stored data in the memory and the grouping corresponds to a block of stored data in the memory. ### Claim 15 (depends on 10) The method of claim 10, further comprising: encoding a series of segments of user data to produce a plurality of extensions of parity bits, each extension of the plurality of extensions of parity bits based on a respective segment in the series; appending each of the plurality of extensions of parity bits to the respective segment to form the serial unit of the encoded data and the plurality of additional serial units of the encoded data, wherein the serial unit and the plurality of additional serial units include a plurality of row codewords; encoding a plurality of derivative segments to produce a plurality of pendent strings of parity bits, each successive bit in each of the plurality of derivative segments correlated to a corresponding sequential position in the serial unit and each of the additional serial units; concatenating individual bits corresponding to consecutive sequential positions in each of the pendent strings of parity bits to form parity segments, the plurality of derivative segments and the corresponding plurality of pendent strings of parity bits forming the plurality of derivative units, wherein each of the plurality of derivative units include a plurality of column codewords; and sending the plurality of row codewords and the plurality of column codewords to the memory. ### Claim 16 (depends on 10) The method of claim 10, wherein the first decoding procedure implements an error correction code and the second decoding procedure implements the error correction code. ### Claim 17 (depends on 10) The method of claim 10, wherein the first decoding procedure implements a first error correction code and the second decoding procedure implements a second error correction code that differs from the first error correction code. ### Claim 18 (depends on 10) The method of claim 10, wherein the memory comprises a plurality of dynamic random-access memory (DRAM) dual in-line memory modules (DIMMs) coupled to a plurality of memory cards configured in accordance with a Peripheral Component Interconnect Express (PCIe or PCI-E) standard. ### Claim 19 A computer program product for detecting and correcting bit errors, comprising: a non-transitory, computer-readable storage medium encoded with instructions adapted to be executed by a processor to implement: performing a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit; determining the first decoding procedure regarding the serial unit was not successful; performing the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units, the serial unit and the plurality of additional serial units comprising a predefined grouping of the encoded data; and performing a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units, each successive bit in each of the plurality of derivative units correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units, wherein the serial unit and the additional serial units each includes a predetermined quantity of sequential bits. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the instructions are further adapted to implement: determining whether or not the second decoding procedure regarding the plurality of derivative units was successful; performing a first iterative decoding procedure regarding a series of serial units corresponding to the plurality of decoded derivative units to produce an updated series of decoded serial units based on having determined the second decoding procedure regarding the plurality of derivative units was not successful; determining whether or not the first iterative decoding procedure regarding the series of serial units was successful; performing a second iterative decoding procedure regarding a second plurality of derivative units to produce an updated plurality of decoded derivative units based on having determined the first iterative decoding procedure regarding the series of serial units was not successful, each successive bit in each of the second plurality derivative units correlated to a corresponding sequential position in each of the updated series of decoded serial units; continuing to perform the first iterative decoding procedure regarding successive resulting series of serial units and the second iterative decoding procedure regarding successive resulting derivative units until the encoded data is successfully decoded; and sending the decoded serial unit corresponding to the successful resulting series of serial units to a host computer.