# US 2017/0288697 A1 · Ldpc shuffle decoder with initialization circuit comprising ordered set memory

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- Number: US 2017/0288697 A1
- Document ID: US20170288697A1
- Status: Published application
- Kind: A1
- Application number: 15/088,055
- Filed: 2016-03-31
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Applicants: Silicon Motion Inc.
- Inventors: Yu-Luen Wang
- Web page: https://patentgrep.com/patent/US20170288697A1

## CPC

- H03M 13/114: {Shuffled, staggered, layered or turbo decoding schedules}
- H03M 13/3723: {using means or methods for the initialisation of the decoder}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding includes: an input wrapper, for receiving input data and padding the input data; an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data to generate channel values corresponding to the padded input data, and outputting a hard decision channel value in a final iteration; and an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder.

## Claims

### Claim 1

A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding, comprising:
an input wrapper, for receiving input data comprising a plurality of codewords and error-correction information, and padding the input data;
an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data according to the error-correction information to generate channel values, and outputting a hard decision channel value in a final iteration; and
an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder, so that the error-correction information can be used to perform LDPC decoding upon the padded input data in the first iteration.

### Claim 2 (depends on 1)

The LDPC decoding apparatus of claim 1, wherein in the first iteration, a sign of the input data is directly input to the LDPC decoder.

### Claim 3 (depends on 1)

The LDPC decoding apparatus of claim 1, wherein the initialization circuit comprises:
a multiplexer, for multiplexing the input data into the ordered set data; and
an ordered set memory, for storing the multiplexed input data as the ordered set data and transmitting the ordered set data to the LDPC decoder.

### Claim 4 (depends on 3)

The LDPC decoding apparatus of claim 3, wherein the LDPC decoder comprises an ordered set memory for receiving the ordered set data from the ordered set memory of the initialization circuit.

### Claim 5 (depends on 4)

The LDPC decoding apparatus of claim 4, wherein the ordered set memory of the LDPC decoder is initially empty before the first iteration, and is then updated in each subsequent iteration.

### Claim 6 (depends on 1)

The LDPC decoding apparatus of claim 1, wherein a bus width of the input data is much smaller than a bus width inside the LDPC decoder.

### Claim 7

A method for performing shuffle decoding in a low-density parity check (LDPC) decoding apparatus, comprising:
receiving input data comprising a plurality of codewords and error-correction information;
padding the input data;
performing a plurality of iterations of LDPC decoding upon the padded input data according to the error-correction information to generate channel values, wherein in a first iteration, the method further comprises:
utilizing an initialization circuit to store the input data into an ordered set data; and
immediately sending the ordered set data to an LDPC decoder of the LDPC decoding apparatus; and
outputting a hard decision channel value in a final iteration.

### Claim 8 (depends on 7)

The method of claim 7, wherein in the first iteration, the method further comprises:
directly inputting a sign of the input data to the LDPC decoder.

### Claim 9 (depends on 7)

The method of claim 7, wherein the step of storing the input data into an ordered set data further comprises:
multiplexing the input data into the ordered set data; and
storing the ordered set data into an ordered set memory of the initialization circuit.

### Claim 10 (depends on 9)

The method of claim 9, wherein the LDPC decoder comprises an ordered set memory for receiving the ordered set data from the ordered set memory of the initialization circuit.

### Claim 11 (depends on 10)

The method of claim 10, wherein the ordered set memory of the LDPC decoder is initially empty before the first iteration, and is then updated in each subsequent iteration.

### Claim 12 (depends on 7)

The method of claim 7, wherein a bus width of the input data is much smaller than a bus width inside the LDPC decoder.