# US 2017/0288684 A1 · Processing apparatus and processing system

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- Number: US 2017/0288684 A1
- Document ID: US20170288684A1
- Status: Published application
- Kind: A1
- Application number: 15/624,931
- Filed: 2017-06-16
- Published: 2017-10-05
- Earliest claimed: 2015-06-30
- Assignees: Olympus Corporation
- Applicants: Olympus Corporation
- Inventors: Tomoharu OGIHARA
- Web page: https://patentgrep.com/patent/US20170288684A1

## CPC

- H03L 7/095: using a lock detector (H03L7/087 takes precedence)
- G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)}
- H03K 19/17716: {with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register (H03K19/17712 takes precedence)}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A processing apparatus includes an FPGA unit connected to an oscillator configured to output a first clock, wherein the FPGA unit includes: a PLL circuit configured to output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock and configured to output a lock signal (detection signal); an input and output monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output an abnormal signal when the detected ratio does not coincide with the predetermined ratio; and an initialization unit configured to output a reset signal when the input and output monitoring unit outputs the abnormal signal and configured to output the reset signal when the PLL circuit outputs the lock signal.

## Claims

### Claim 1

A processing apparatus comprising:
a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and
a memory storing circuit information of the programmable logic circuit, wherein
the programmable logic circuit comprises:
a phase synchronization circuit configured to generate and output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock based on the first clock;
a detection unit provided on the phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined detection signal;
an arithmetic unit configured to execute a predetermined process based on the second clock;
a monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output a predetermined abnormal signal when the detected ratio does not coincide with the predetermined ratio; and
an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the detection unit outputs the detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in either case.

### Claim 2

A processing apparatus comprising:
a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and
a memory storing circuit information of the programmable logic circuit, wherein
the programmable logic circuit comprises:
a phase synchronization circuit configured to generate and output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock based on the first clock;
a detection unit provided on the phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined detection signal;
an arithmetic unit configured to execute a predetermined process based on the second clock;
a monitoring unit configured to compare two adjacent clock signals in the second clock and output a predetermined abnormal signal when detecting a predetermined phase difference; and
an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the detection unit outputs the detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in either case.

### Claim 3

A processing apparatus comprising:
a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and
a memory storing circuit information of the programmable logic circuit, wherein
the programmable logic circuit comprises:
a first phase synchronization circuit configured to generate and output a second clock with a frequency of a first predetermined ratio with respect to a frequency of the first clock based on the first clock;
a second phase synchronization circuit configured to generate and output a third clock with a frequency of a second predetermined ratio with respect to the frequency of the first clock based on the first clock;
a first detection unit provided on the first phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined first detection signal;
a second detection unit provided on the second phase synchronization circuit and configured to detect an asynchronous state of the first clock and the third clock to output a predeteiiiiined second detection signal;
an arithmetic unit comprising a first arithmetic circuit configured to execute a predetermined process based on the second clock and a second arithmetic circuit configured to execute a predetermined process based on the third clock;
a monitoring unit configured to output a predetermined abnormal signal when at least one of the second clock and the third clock is in a predetermined abnormal state; and
an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the first detection unit outputs the first detection signal, further generate the reset signal when the second detection unit outputs the second detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in any case.

### Claim 4 (depends on 3)

The processing apparatus according to claim 3, wherein
the monitoring unit outputs the abnormal signal when the monitoring unit detects a ratio between the frequencies of the first clock and the second clock, and the detected ratio does not coincide with the first predetermined ratio, and/or when the monitoring unit detects a ratio between the frequencies of the first clock and the third clock, and the detected ratio does not coincide with the second predetermined ratio.

### Claim 5 (depends on 1)

A processing system comprising:
the processing apparatus according to claim 1; and
the oscillator configured to output the first clock to the programmable logic circuit.

### Claim 6 (depends on 2)

A processing system comprising:
the processing apparatus according to claim 2; and
the oscillator configured to output the first clock to the programmable logic circuit.

### Claim 7 (depends on 3)

A processing system comprising:
the processing apparatus according to claim 3; and
the oscillator configured to output the first clock to the programmable logic circuit.