# US 2017/0288683 A1 · Coarse delay lock estimation for digital dll circuits

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- Number: US 2017/0288683 A1
- Document ID: US20170288683A1
- Status: Published application
- Kind: A1
- Application number: 15/089,523
- Filed: 2016-04-02
- Published: 2017-10-05
- Earliest claimed: 2016-04-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Fangxing Wei; Khushal Chandan; Dan Shi; Michael Allen
- Web page: https://patentgrep.com/patent/US20170288683A1

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- H03L 7/0818: {the controlled phase shifter comprising coarse and fine delay or phase-shifting means}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/10: for assuring initial synchronisation or for broadening the capture range
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

## Claims

### Claim 1

An electronic device, comprising:
delay-locked loop (DLL) circuitry configured to:
receive a reference clock signal from a reference clock source;
compare a number of positive clock edges of the reference clock signal to a number of negative clock edges of the reference clock signal within an initial delay test window;
increase the duration of the initial delay test window by a delay increment if the number of positive clock edges does not equal the number of negative clock edges;
repeat receipt of the reference clock signal, comparison of the number of positive to negative clock edges, and increase the duration of the delay test window until the number of positive and negative clock edges in the delay test window are equal; and
coarse lock a strobe signal to the reference clock signal with a coarse delay equal to a total duration increase of the delay test window.

### Claim 2 (depends on 1)

The device of claim 1, wherein the DLL circuitry is further configured to:
maintain the locking of the strobe signal to the reference clock signal with a closed negative feedback loop.

### Claim 3 (depends on 1)

The device of claim 1, further comprising a double data rate (DDR) compatible interface coupled to the DLL circuitry.

### Claim 4 (depends on 3)

The device of claim 3, wherein the initial delay test window has a duration equal to the DDR interface analog delay path.

### Claim 5 (depends on 1)

The device of claim 1, wherein the delay increment is a duration of at least one reference clock cycle.

### Claim 6 (depends on 1)

The device of claim 1, wherein, to compare the number of positive to negative clock edges, the DLL circuitry is further configured to:
pass the reference clock signal through a pair of shift registers, where one shift register is triggered on positive clock edges and the other shift register is triggered on negative clock edges; and
compare, using a compare circuit, the number of positive clock edges passing through one of the pair of shift registers to the number of negative clock edges passing through the other of the pair of shift registers during the delay test window.

### Claim 7 (depends on 6)

The device of claim 6, wherein the DLL circuitry is further configured to:
send a start transition to the pair of shift registers to start the delay test window; and
send the start transition through an analog delay path and to the pair of shift registers to stop the delay test window.

### Claim 8

A delay locked-loop (DLL) circuit, comprising:
a closed loop fine delay tracking circuit;
a variable delay circuit;
an open loop coarse delay matching circuit to determine a coarse delay code by testing a current coarse delay code, further comprising:
a pair of shift registers each comprised of a plurality of flip flops configured such that one of the pair of shift registers is responsive to positive clock edges and the other is responsive to negative clock edges;
a reference clock input to each flip flop;
a compare circuit coupled between the pair of shift registers;
a state machine coupled to a first flip flop of each of the pair of shift registers, and configured to introduce a high value into each first flip flop; and
a reference clock delay loop coupled from the reference clock input through the variable delay circuit to each flip flop, and configured to de-activate the pluralities of flip flops.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the state machine is configured to:
hold the current coarse delay code; and
update the current coarse delay code when, upon inactivation of the pluralities of flip flops, a match state is low from the compare circuit.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the update to the current coarse delay is an increase of the duration of the current coarse delay.

### Claim 11 (depends on 8)

The circuit of claim 8, wherein the pair of shift registers are configured to shift the high value along each shift register with each cycle of the reference clock, wherein each shift register holds a value representing the number of positive or negative clock edges experienced by the respective shift register.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the compare circuit is configured to:
compare the value stored in each shift register upon inactivation of the pluralities of flip flops; and
output a match signal to the state machine when the values stored in each shift register are equal.

### Claim 13 (depends on 12)

The circuit of claim 12, wherein the state machine, in response to receipt of a match signal, is further configured to:
lock the DLL circuit with the current coarse delay code; and
activate the fine delay tracking circuit.

### Claim 14 (depends on 8)

The circuit of claim 8, further comprising a dummy delay circuit coupled in the reference clock delay loop between the variable delay circuit and the pluralities of flip flops.

### Claim 15

An open loop coarse delay matching circuit, comprising:
a variable delay circuit;
a pair of shift registers each comprised of a plurality of flip flops configured such that one of the pair of shift registers is responsive to positive clock edges and the other is responsive to negative clock edges;
a reference clock input to each flip flop;
a compare circuit coupled between the pair of shift registers;
a state machine coupled to a first flip flop of each of the pair of shift registers, and configured to introduce a high value into each first flip flop; and
a reference clock delay loop coupled from the reference clock input through the variable delay circuit to each flip flop, and configured to de-activate the pluralities of flip flops.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein the state machine is configured to:
hold the current coarse delay code; and
update the current coarse delay code when, upon inactivation of the pluralities of flip flops, a match state is low from the compare circuit.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the update to the current coarse delay is an increase of the duration of the current coarse delay.

### Claim 18 (depends on 15)

The circuit of claim 15, wherein the pair of shift registers are configured to shift the high value along each shift register with each cycle of the reference clock, wherein each shift register holds a value representing the number of positive or negative clock edges experienced by the respective shift register.

### Claim 19 (depends on 18)

The circuit of claim 18, wherein the compare circuit is configured to:
compare the value stored in each shift register upon inactivation of the pluralities of flip flops; and
output a match signal to the state machine when the values stored in each shift register are equal.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the state machine, in response to receipt of a match signal, is further configured to:
lock the DLL circuit with the current coarse delay code; and
activate a fine delay tracking circuit.

### Claim 21 (depends on 15)

The circuit of claim 15, further comprising a dummy delay circuit coupled in the reference clock delay loop between the variable delay circuit and the pluralities of flip flops.

### Claim 22 (depends on 8)

A computing system, comprising:
a processor;
a memory;
a memory interface comprising a delay locked-loop (DLL) circuit as in claim 8; and
a memory controller coupled to the processor and to the memory through the memory interface.

### Claim 23 (depends on 22)

The system of claim 22, wherein the state machine is configured to:
hold the current coarse delay code; and
update the current coarse delay code when, upon inactivation of the pluralities of flip flops, a match state is low from the compare circuit.

### Claim 24 (depends on 22)

The system of claim 22, wherein the pair of shift registers are configured to shift the high value along each shift register with each cycle of the reference clock, wherein each shift register holds a value representing the number of positive or negative clock edges experienced by the respective shift register.

### Claim 25 (depends on 22)

The system of claim 22, further comprising a dummy delay circuit coupled in the reference clock delay loop between the variable delay circuit and the pluralities of flip flops.

### Claim 26 (depends on 22)

The system of claim 22, wherein the memory interface is a double data rate (DDR) compatible interface and the memory is a DDR-compliant memory.