# US 2017/0288680 A1 · Crystal oscillator circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288680 A1 - Document ID: US20170288680A1 - Status: Published application - Kind: A1 - Application number: 15/436,892 - Filed: 2017-02-20 - Published: 2017-10-05 - Earliest claimed: 2016-03-30 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Inventors: Er Yuan FENG; Zhen Jiang SU; Zhen Ye GUO - Web page: https://patentgrep.com/patent/US20170288680A1 ## CPC - H03L 3/00: Starting of generators - H03B 5/06: Modifications of generator to ensure starting of oscillations - H03B 5/32: being a piezoelectric resonator (selection of piezoelectric material H10N30/00) - H03B 5/364: {the amplifier comprising field effect transistors (H03B5/366 takes precedence)} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03B 2200/0082: Lowering the supply voltage and saving power - H03B 2200/0094: Measures to ensure starting of oscillations - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A crystal oscillator circuit is provided. The crystal oscillator circuit includes an oscillator start-up circuit having a first output terminal and a second output terminal, where the second output terminal outputs a first oscillation signal; and a waveform conversion circuit configured to convert the first oscillation signal to a rectangular wave signal. The crystal oscillator circuit also includes a first current source configured to output a first current to drive the oscillator start-up circuit; and a second current source configured to output a second current, and being connected in parallel with the first current source to jointly drive the oscillator start-up circuit. Further the crystal oscillator circuit includes a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time. ## Claims ### Claim 1 A crystal oscillator circuit, comprising: an oscillator start-up circuit having a first output terminal and a second output terminal, wherein the second output terminal outputs a first oscillation signal: waveform conversion circuit configured to convert the first oscillation signal to a rectangular wave signal; a first current source configured to output a first current to drive the oscillator start-up circuit; a second current source configured to output a second current, and being connected in parallel with the first current source to jointly drive the oscillator start-up circuit; and a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time. ### Claim 2 (depends on 1) The crystal oscillator circuit according to claim 1, wherein the oscillator start-up circuit includes: a crystal oscillator, wherein a first output terminal and a second output terminal of the crystal oscillator are respectively connected to the first output terminal and the second output terminal of the oscillator start-up circuit; a first load capacitor, wherein a first terminal of the first load capacitor is connected to the first output terminal of the oscillator start-up circuit, and a second terminal of the first load capacitor is grounded; a second load capacitor, wherein a first terminal of the second load capacitor is connected to the second output terminal of the oscillator start-up circuit, and a second terminal of the second load capacitor is grounded; and an inverter, wherein an input terminal and an output terminal of the inverter are respectively connected to the first output terminal and the second output terminal of the oscillator start-up circuit. ### Claim 3 (depends on 1) The crystal oscillator circuit according to claim 1, wherein the pulse generation circuit includes: a charging circuit having a charging node, wherein, when the power is turned on, a power supply charges the charging circuit, and the charging node outputs a first pulse signal; an edge adjustment circuit configured to improve the edge sharpness of the first pulse signal to obtain a second pulse signal; a delay circuit configured to delay the second pulse signal to output a third pulse signal; and a logic circuit configured to perform a logic operation onto the second pulse signal and the third pulse signal to output the control pulse signal. ### Claim 4 (depends on 3) The crystal oscillator circuit according to claim 3, wherein the charging circuit includes: a first resistor; and a third, capacitor, wherein a first terminal of the first resistor is connected to the power supply; a second terminal of the first resistor is connected to a first terminal of the third capacitor and connected to the charging node; and a second terminal of the third capacitor is grounded. ### Claim 5 (depends on 3) The crystal oscillator circuit according to claim 3, wherein: the edge adjustment circuit includes a cascade of at least one buffer. ### Claim 6 (depends on 3) The crystal oscillator circuit according to claim 3, wherein: the delay circuit includes even number of cascaded inverters. ### Claim 7 (depends on 3) The crystal oscillator circuit according to claim 3, wherein: the logic circuit is an AND gate; a first input terminal and a second input terminal of the AND gate respectively input, the second pulse signal and the third pulse signal; and an output terminal of the AND gate outputs the control pulse signal. ### Claim 8 (depends on 2) The crystal oscillator circuit according to claim 2, wherein the inverter includes: a first PMOS transistor; and a first NMOS transistor, wherein a gate of the first PMOS transistor is connected to a gate of the first NMOS transistor and connected to the input terminal of the inverter; a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and connected to the output terminal of the inverter; a source of the first NMOS transistor is grounded; and a source of the first PMOS transistor is connected to an output terminal of the first current source and the second current source. ### Claim 9 (depends on 1) The crystal oscillator circuit according to claim 1, wherein the second current source includes: a second PMOS transistor; a source of the second PMOS transistor is connected to the power supply; a gate of the second PMOS transistor inputs the control pulse signal; and a drain of the second PMOS transistor is as the output terminal of the second current source. ### Claim 10 (depends on 1) The crystal oscillator circuit according to claim 1, wherein: the waveform conversion circuit includes a cascade of at least one buffer. ### Claim 11 (depends on 1) The crystal oscillator circuit according to claim 1, wherein: a source of the first PMOS transistor is connected to an output terminal of the first current source and the second current source. ### Claim 12 A method for driving a crystal oscillator circuit, comprising: providing an oscillator start-up circuit having a first output terminal and a second output terminal; providing a first current source configured to output a first current; providing a second current source configured to output a second current; and proving a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time. ### Claim 13 (depends on 12) The method according to claim 12, wherein: the second current source is in parallel with the first current source to jointly drive the oscillator start-up circuit, to increase the ability to drive the oscillator start-up circuit without changing the loop-gain of the crystal oscillator circuit and to decrease the start-up time of the crystal oscillator circuit. ### Claim 14 (depends on 12) The method according to claim 12, wherein: the second current source only operates for the preset time when the crystal oscillator circuit is turned on, to reduce the start-up time of circuit, at the same time, to ensure the low-power consumption characteristic of the circuit. ### Claim 15 (depends on 12) The method according to claim 12, wherein forming the pulse generation circuit includes: providing a charging circuit having a charging node, wherein, when the power is turned on, a power supply charges the charging circuit, and the charging node outputs a first pulse signal; providing an edge adjustment circuit configured to improve the edge sharpness of the first pulse signal to obtain a second pulse signal; providing a delay circuit configured to delay the second pulse signal to output a third pulse signal; and providing a logic circuit configured to perform a logic operation onto the second pulse signal and the third pulse signal to output the control pulse signal. ### Claim 16 (depends on 15) The method according to claim 15, wherein forming the charging circuit includes: providing a first resistor; and providing a third capacitor, wherein a first terminal of the first resistor is connected to the power supply; a second terminal of the first resistor is connected to a first terminal of the third capacitor and connected to the charging node; and a second terminal of the third capacitor is grounded, ### Claim 17 (depends on 15) The method according to claim 15, wherein: the edge adjustment circuit includes a cascade of at least one buffer. ### Claim 18 (depends on 15) The method according to claim 15, wherein: the delay circuit includes even number of cascaded inverters. ### Claim 19 (depends on 15) The method according to claim 15 wherein: the logic circuit is an AND gate: a first input terminal and a second input terminal of the AND gate respectively input the second pulse signal and the third pulse signal; and an output terminal of the AND gate outputs the control pulse signal. ### Claim 20 (depends on 12) The method according to claim 12, wherein fanning the second current source includes: providing a second PMOS transistor; a source of the second PMOS transistor is connected to the power supply; a gate of the second PMOS transistor inputs the control pulse signal; and a drain of the second PMOS transistor is as the output terminal of the second current source.